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IMX53IEC Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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IMX53IEC Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 173 page  Modules List i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 7 3 Modules List The i.MX53 processor contains a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Table 2. i.MX53 Digital and Analog Blocks Block Mnemonic Block Name Subsystem Brief Description ARM ARM Platform ARM The ARM CortexTM A8 platform consists of the ARM processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache. The platform also contains an event monitor and debug modules. It also has a NEON coprocessor with SIMD media processing architecture, a register file with 32/64-bit general-purpose registers, an integer execute pipeline (ALU, Shift, MAC), dual single-precision floating point execute pipelines (FADD, FMUL), a load/store and permute pipeline and a non-pipelined vector floating point (VFP Lite) coprocessor supporting VFPv3. ASRC Asynchronous Sample Rate Converter Multimedia Peripherals The asynchronous sample rate converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about -120 dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs. AUDMUX Digital Audio Multiplexer Multimedia Peripherals The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports. CAMP-1 CAMP-2 Clock Amplifier Clocks, Resets, and Power Control Clock amplifier CCM GPC SRC Clock Control Module Global Power Controller System Reset Controller Clocks, Resets, and Power Control These modules are responsible for clock and reset distribution in the system, as well as for system power management. The system includes four PLLs. CSPI ECSPI-1 ECSPI-2 Configurable SPI, Enhanced CSPI Connectivity Peripherals Full-duplex enhanced synchronous serial interface, with data rates 16-60 Mbit/s. It is configurable to support master/slave modes. In Master mode it supports four slave selects for multiple peripherals. CSU Central Security Unit Security The central security unit (CSU) is responsible for setting comprehensive security policy within the i.MX53 platform, and for sharing security information between the various security modules. The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. |
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