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IMX53IEC Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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IMX53IEC Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 173 page  Introduction i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 5 — Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer (AUDMUX) providing four external ports. — Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support 4-wire. — Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port — Three I2C ports, supporting 400 kbps — Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps — Two controller area network (FlexCAN) interfaces, 1 Mbps each — Sony Phillips Digital Interface (SPDIF), Rx and Tx — Key pad port (KPP) — Two pulse-width modulators (PWM) — GPIO with interrupt capabilities The system supports efficient and smart power control and clocking: • Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes • Power gating SRPG (State Retention Power Gating) for ARM core and Neon • Support for various levels of system power modes • Flexible clock gating control scheme • On-chip temperature monitor • On-chip oscillator amplifier supporting 32.768 kHz external crystal • On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware/features: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on) • Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features • Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches • Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine • SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator (TRNG) • Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure RAM and support for multiple keys as well as TZ/non-TZ separation • Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is configured during boot by eFUSEs, and determines the security level operation mode as well as the TrustZone (TZ) policy • Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization • Tamper detection mechanism—Provides evidence of any physical attempt to remove the device cover. Upon detection of such an attack, sensitive information can immediately be erased. |
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