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AD1671KQ Datasheet(PDF) 10 Page - Analog Devices |
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AD1671KQ Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page AD1671 REV. B –10– UNIPOLAR (0 V TO +2.5 V) CALIBRATION The connections for the 0 V to +2.5 V input range calibration is shown in Figure 11. Figure 11 shows an example of how the offset error can be trimmed in front of the AD1671. The proce- dure for trimming the offset and gain errors is the same as for the unipolar 5 V range. AIN1 AIN2 5k 5k SHA OUT BPO/UPO AD1671 REF IN REF OUT SHA OFFSET ADJ +15V 1k 0 TO +2.5V VIN 10k 10k R2 2k GAIN ADJ 1µF R1 AD845 1k Ω 390 Ω Figure 11. Unipolar (0 V to +2.5 V) Calibration BIPOLAR ( 2.5 V) CALIBRATION The connections for the bipolar ±2.5 V input range is shown in Figure 12. AIN1 AIN2 5k 5k SHA OUT BPO/UPO AD1671 REF IN REF OUT SHA OFFSET ADJ +15V 1k VIN 10k 10k R2 2k GAIN ADJ 1µF R1 AD845 1k Ω 390 Ω –2.5V TO +2.5V Figure 12. Bipolar ( ±2.5 V) Calibration OUTPUT LATCHES Figure 13 shows the AD1671 connected to the 74HC574 octal D-type edge-triggered latches with 3-state outputs. The latch can drive highly capacitive loads (i.e., bus lines, I/O ports) while maintaining the data signal integrity. The maximum setup and hold times of the 574 type latch must be less than 20 ns (tDD and tSS minimum). To satisfy the requirements of the 574 type latch the recommended logic families are S, AS, ALS, F or BCT. New data from the AD1671 is latched on the rising edge of the DAV (Pin 16) output pulse. Previous data can be latched by inverting the DAV output with a 7404 type inverter. BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 DAV DATA BUS 3-STATE CONTROL AD1671 1D 2D 3D 4D 5D 6D 7D 8D CLOCK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 74HC574 OC 1D 2D 3D 4D 5D 6D 7D 8D CLOCK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 74HC574 OC Figure 13. AD1671 to Output Latches OUT OF RANGE An out-of-range condition exists when the analog input voltage is beyond the input range (0 V to +2.5 V, 0 V to +5 V, ±2.5 V, ±5 V) of the converter OTR (Pin 15) is set low when the analog input voltage is within the analog input range. OTR is set HIGH and will remain HIGH when the analog input voltage exceeds the input range by typically 1/2 LSB (OTR transition is tested to ±6 LSBs of accuracy) from the center of the ±full-scale output codes. OTR will remain HIGH until the analog input is within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table II is a truth table for the over/under range circuit in Figure 14. Sys- tems requiring programmable gain conditioning prior to the AD1671 can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Table II. Out-of-Range Truth Table OTR MSB Analog Input Is 0 0 In Range 0 1 In Range 1 0 Underrange 1 1 Overrange MSB OTR MSB OVER = "1" UNDER = "1" Figure 14. Overrange or Underrange Logic |
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