R1LV0416D Series

Write Cycle

R1LV0416D

-5SI

-7LI

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

55



70



ns

Address valid to end of write

t

AW

50



60



ns

Chip selection to end of write

t

CW

50



60



ns

5

Write pulse width

t

WP

40



50



ns

4

LB#, UB# valid to end of write

t

BW

50



55



ns

Address setup time

t

AS

0



0



ns

6

Write recovery time

t

WR

0



0



ns

7

Data to write time overlap

t

DW

25



30



ns

Data hold from write time

t

DH

0



0



ns

Output active from end of write

t

OW

5



5



ns

2

Output disable to output in high-Z

t

OHZ

0

20

0

25

ns

1, 2, 3

Write to output in high-Z

t

WHZ

0

20

0

25

ns

1, 2

Notes: 1. t

referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. At any given temperature and voltage condition, t

device to device.

4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write

begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB#

going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and

LB# going high or UB# going high. t

5. t

6. t

7. t

Rev.1.00, May.24.2007, page 9 of 15