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IS43DR16320B-3DBL Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS43DR16320B-3DBL Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
6 / 30 page IS43/46DR86400B, IS43/46DR16320B Integrated Silicon Solution, Inc. – www.issi.com – 6 Rev. I, 8/01/2012 Mode Register (MR) Diagram A12 0 BA1 0 1 BA0 0 A13(1) 0 A11 A10 A9 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A8 0 A7 1 0 1 A6 A5 A4 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A3 0 1 A2 A1 A0 BL 0 1 0 4 0 1 1 8 Address Field Mode Register A2 Burst Length Reserved A1 Burst Type Sequential A0 Interleave A3 BT 5 6 A6 CAS Latency CAS Latency Reserved A5 Reserved Reserved A4 3 4 A7 TM Yes Reserved A8 DLL DLL Reset Mode No Normal A11 WR 4 5 A10 6 Reserved A9 Reserved Reserved A12 PD1 2 3 WR(cycles)(2) Slow exit(use tXARDS) Active power down exit time Fast exit (use tXARD) Notes: 1. A13 is reserved for future use and must be set to 0 when programming the MR. 2. The minimum value for WR(write recovery for autoprecharge) is determined by tCK(Max) and maximum value for WR is determined by tCK(Min). WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL. DDR2 Extended Mode Register 1 (EMR[1]) Setting The extended mode register 1 stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. Extended mode register 1 is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1 and HIGH on BA0, and controlling pins A0 - A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling reduced strength data-output driver. A3 - A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7 - A9 are used for OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable. |
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