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HEF4013BT Datasheet(PDF) 4 Page - NXP Semiconductors |
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HEF4013BT Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 17 page HEF4013B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 21 November 2011 4 of 16 NXP Semiconductors HEF4013B Dual D-type flip-flop 8. Limiting values [1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. [2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. [3] For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K. 9. Recommended operating conditions Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +18 V IIK input clamping current VI < 0.5 V or VI >VDD + 0.5 V - 10 mA VI input voltage 0.5 VDD + 0.5 V IOK output clamping current VO < 0.5 V or VO >VDD + 0.5 V - 10 mA II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation Tamb = 40 C to +125 C DIP14 [1] - 750 mW SO14 [2] - 500 mW TSSOP14 [3] - 500 mW P power dissipation per output - 100 mW Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VDD supply voltage 3 15 V VI input voltage 0 VDD V Tamb ambient temperature 40 +125 C t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V VDD = 10 V - 0.5 s/V VDD = 15 V - 0.08 s/V |
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