Supertex inc.

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

VN10K

Features

Applications

memories, displays, bipolar transistors, etc.)

General Description

This enhancement-mode (normally-off) transistor utilizes a

vertical DMOS structure and Supertex’s well-proven, silicon-

gate manufacturing process. This combination produces a

devicewiththepowerhandlingcapabilitiesofbipolartransistors

and the high input impedance and positive temperature

coefficient inherent in MOS devices. Characteristic of all

MOS structures, this device is free from thermal runaway and

thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching speeds

are desired.

N-Channel Enhancement-Mode

Vertical DMOS FET

Ordering Information

Device

Package

BV

(V)

R

DS(ON)

(max)

(Ω)

I

D(ON)

(min)

(mA)

TO-92

VN10K

VN10KN3-G

60

5.0

750

Pin Configuration

TO-92 (N3)

GATE

SOURCE

DRAIN

YY = Year Sealed

WW = Week Sealed

= “Green” Packaging

SiVN

10K

YYWW

TO-92 (N3)

Product Marking

Package may or may not include the following marks: Si or

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±30V

Operating and storage temperature

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

Absolute Maximum Ratings

For packaged products, -G indicates package is RoHS compliant (‘Green’).

Consult factory for die / wafer form part numbers.

Refer to Die Specification VF21 for layout and dimensions.