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S29JL032J70TFI223 Datasheet(PDF) 8 Page - SPANSION |
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S29JL032J70TFI223 Datasheet(HTML) 8 Page - SPANSION |
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8 / 63 page  8 S29JL032J S29JL032J_00_06 December 16, 2011 Data She e t 1. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into separate banks (see Table 8.2 on page 17). Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The S29JL032J can be organized with either a top or bottom boot sector configuration. 1.1 S29JL032J Features The Secured Silicon Region is an extra 256 byte sector capable of being permanently locked by the customer. The Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been locked and is 0 if lockable. Customers may utilize the Secured Silicon Region as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. The device offers complete compatibility with the JEDEC 42.4 single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Region area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. |
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