S25FL128SAGMFVG13 datasheet(10/153 Pages) SPANSION

Part #	S25FL128SAGMFVG13

Description	MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

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Manufacturer	SPANSION [SPANSION]

Direct Link	http://www.spansion.com

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10 / 153 page

10

S25FL128S and S25FL256S

S25FL128S_256S_00_05 July 12, 2012

Da ta

Sh e e t

Tables

Table 1.1

Maximum Read Rates with the Same Core and I/O Voltage (VIO = VCC = 2.7V to 3.6V) . . . . 4

Table 1.2

Maximum Read Rates with Lower I/O Voltage (VIO = 1.65V to 2.7V, VCC = 2.7V to 3.6V) . . . 4

Table 1.3

Maximum Read Rates DDR (VIO = VCC = 3V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1.4

Typical Program and Erase Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1.5

Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2.1

FL Generations Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3.1

Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.1

Interface States Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 5.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 5.2

Power-up/Power-down Voltage and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 5.3

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 6.1

AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 6.2

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6.3

Hardware Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 6.4

AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . 40

Table 6.5

AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V). . . . . . . . . . 41

Table 6.6

AC Characteristics 66 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 7.1

Model Specific Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 8.1

S25FL256S Sector and Memory Address Map, Bottom 4-kbyte Sectors . . . . . . . . . . . . . . . 54

Table 8.2

S25FL256S Sector and Memory Address Map, Top 4-kbyte Sectors . . . . . . . . . . . . . . . . . . 55

Table 8.3

S25FL256S Sector and Memory Address Map, Uniform 256-kbyte Sectors . . . . . . . . . . . . . 55

Table 8.4

S25FL128S Sector and Memory Address Map, Bottom 4-kbyte Sectors . . . . . . . . . . . . . . . 55

Table 8.5

S25FL128S Sector and Memory Address Map, Top 4-kbyte Sectors . . . . . . . . . . . . . . . . . . 55

Table 8.6

S25FL128S Sector and Memory Address Map, Uniform 256-kbyte Sectors . . . . . . . . . . . . . 55

Table 8.7

OTP Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 8.8

Status Register-1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 8.9

Configuration Register (CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 8.10

Latency Codes for SDR High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 8.11

Latency Codes for DDR High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 8.12

Latency Codes for SDR Enhanced High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 8.13

Latency Codes for DDR Enhanced High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 8.14

Status Register-2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 8.15

AutoBoot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 8.16

Bank Address Register (BAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 8.17

ASP Register (ASPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 8.18

Password Register (PASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 8.19

PPB Lock Register (PPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 8.20

PPB Access Register (PPBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 8.21

DYB Access Register (DYBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 8.22

Non-Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 8.23

Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 9.1

Upper Array Start of Protection (TBPROT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 9.2

Lower Array Start of Protection (TBPROT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 9.3

Sector Protection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 10.1

Bank Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 10.2

S25FL128S and S25FL256S Command Set (sorted by function) . . . . . . . . . . . . . . . . . . . . . 75

Table 10.3

Read_ID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 10.4

RES Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 10.5

Block Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 10.6

Commands Allowed During Program or Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 10.7

Program and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 10.8

Program Suspend AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 10.9

Erase Suspend AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 11.1

S25FL128S and S25FL256S Instruction Set (sorted by instruction) . . . . . . . . . . . . . . . . . . 131

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