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TMS320C6204ZHK200 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6204ZHK200 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 95 page TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 D High-Performance Fixed-Point Digital Signal Processor (DSP) -- TMS320C6204 -- 5-ns Instruction Cycle Time -- 200-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1600 MIPS D C6204 GLW Ball Grid Array (BGA) Package is Pin-Compatible With the C6202/02B/03 GLS BGA Package† D VelociTI™ Advanced Very-Long-Instruction- Word (VLIW) TMS320C62x™ DSP Core -- Eight Highly Independent Functional Units: -- SixALUs(32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Result) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) -- Organized as Two 32K-Byte Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Synchronous Memories: SDRAM or SBSRAM -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- 52M-Byte Addressable External Memory Space D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D 32-Bit Expansion Bus (XB) -- Glueless/Low-Glue Interface to Popular PCI Bridge Chips -- Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses -- Master/Slave Functionality -- Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals D Two Multichannel Buffered Serial Ports (McBSPs) -- Direct Interface to T1/E1, MVIP, SCSA Framers -- ST-Bus-Switching Compatible -- Up to 256 Channels Each -- AC97-Compatible -- Serial-Peripheral Interface (SPI) Compatible (Motorola™) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked-Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG‡) Boundary-Scan-Compatible D 288-Pin MicroStar BGA™ Package (GHK) D 340-Pin BGA Package (GLW) D 0.15-μm/5-Level Metal Process -- CMOS Technology D 3.3-V I/Os, 1.5-V Internal PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † For more details, see the GLW BGA package bottom view. ‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright © 2004, Texas Instruments Incorporated |
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