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Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

Cyclone IV Device Handbook,

November 2011

Altera Corporation

Volume 1

Cyclone IV Device Family Architecture

This section describes Cyclone IV device architecture and contains the following

topics:

■

“FPGA Core Fabric”

■

“I/O Features”

■

“Clock Management”

■

“External Memory Interfaces”

■

“Configuration”

■

“High-Speed Transceivers (Cyclone IV GX Devices Only)”

■

“Hard IP for PCI Express (Cyclone IV GX Devices Only)”

FPGA Core Fabric

Cyclone IV devices leverage the same core fabric as the very successful Cyclone series

devices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memory

blocks, and multipliers.

Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM

memory. You can configure the M9K blocks as single port, simple dual port, or true

dual port RAM, as well as FIFO buffers or ROM. They can also be configured to

implement any of the data widths in Table 1–7.

The multiplier architecture in Cyclone IV devices is the same as in the existing

Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or

two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP

including finite impulse response (FIR), fast Fourier transform (FFT), and numerically

controlled oscillator (NCO) functions for use with the multiplier blocks. The

MATLAB design environments for a streamlined DSP design flow.

Devices, Memory Blocks in Cyclone IV Devices, and Embedded Multipliers in Cyclone IV

Devices chapters.

Table 1–7. M9K Block Data Widths for Cyclone IV Device Family

Mode

Data Width Configurations

Single port or simple dual port

×1, ×2, ×4, ×8/9, ×16/18, and ×32/36

True dual port

×1, ×2, ×4, ×8/9, and ×16/18