AD9613-170EBZ datasheet(10/36 Pages) AD

Part #	AD9613-170EBZ

Description	12-Bit, 170 MSPS/210 MSPS/250 MSPS,1.8 V Dual Analog-to-Digital Converter (ADC)

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10 / 36 page

AD9613

Data Sheet

Rev. C | Page 10 of 36

Timing Diagrams

VIN

CLK+

CLK–

DCO–

DCO+

D0±

(LSB)

PARALLEL INTERLEAVED

CHANNEL MULTIPLEXED

(EVEN/ODD) MODE

CHANNEL MULTIPLEXED

(EVEN/ODD) MODE

D11±

(MSB)

D0±/D1±

(LSB)

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

CH A0

N – 10

CH A1

N – 10

CH A0

N – 9

CH A1

N – 9

CH A0

N – 8

CH A1

N – 8

CH A0

N – 7

CH A1

N – 7

CH A0

N – 6

CH A10

N – 10

CH A11

N – 10

CH A10

N – 9

CH A11

N – 9

CH A10

N – 8

CH A11

N – 8

CH A10

N – 7

CH A11

N – 7

CH A10

N – 6

CH B0

N – 10

CH B1

N – 10

CH B0

N – 9

CH B1

N – 9

CH B0

N – 8

CH B1

N – 8

CH B0

N – 7

CH B1

N – 7

CH B0

N – 6

CH B10

N – 10

CH B11

N – 10

CH B10

N – 9

CH B11

N – 9

CH B10

N – 8

CH B11

N – 8

CH B10

N – 7

CH B11

N – 7

CH B10

N – 6

CHANNEL A

D10±/D11±

(MSB)

D0±/D1±

(LSB)

CHANNEL B

D10±/D11±

(MSB)

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

tA

tCH

tPD

tSKEW

tDCO

tCLK

.

CHANNEL A AND

CHANNEL B

Figure 2. Interleaved LVDS Mode Data Output Timing

tSSYNC

tHSYNC

SYNC

CLK+

Figure 3. SYNC Timing Inputs

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