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AD5628BCBZ-1-RL7 Datasheet(PDF) 9 Page - Analog Devices

Part # AD5628BCBZ-1-RL7
Description  Octal, 12-/14-/16-Bit SPI Voltage Output denseDAC with 5 ppm/째C On-Chip Reference
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5628BCBZ-1-RL7 Datasheet(HTML) 9 Page - Analog Devices

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Data Sheet
AD5628/AD5648/AD5668
Rev. G | Page 9 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
AD5628/
AD5648/
VDD
VOUTA
VOUTC
VREFIN/VREFOUT
VOUTG
VOUTE
14
13
12
11
10
9
8
DIN
GND
VOUTB
VOUTH
VOUTF
VOUTD
SCLK
TOP VIEW
(Not to Scale)
SYNC
Figure 3. 14-Lead TSSOP (RU-14)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
VDD
VOUTA
VOUTG
VOUTE
VOUTC
LDAC
DIN
GND
VOUTB
VOUTH
VREFIN/VREFOUT
CLR
VOUTF
VOUTD
SCLK
AD5628/
AD5648/
AD5668
TOP VIEW
(Not to Scale)
Figure 4. 16-Lead TSSOP (RU-16)
12
11
10
1
3
4
GND
VOUTB
VOUTD
9
VOUTF
VDD
VOUTC
2
VOUTA
VOUTE
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD MUST BE TIED TO GND.
AD5628/AD5668
Figure 5. 16-Lead LFCSP(CP-16-17)
Table 6. Pin Function Descriptions
Pin No.
14-Lead
TSSOP
16-Lead
TSSOP
16-Lead
LFCSP
Mnemonic
Description
N/A
1
15
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively, this
pin can be tied permanently low.
1
2
16
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift
register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken
high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.
2
3
1
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply
should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
3
4
2
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
11
13
11
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4
5
3
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
10
12
10
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7
8
6
VREFIN/
VREFOUT
The AD5628/AD5648/AD5668 have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When using
an external reference, this is the reference input pin. The default for this pin is as a
reference input.
N/A
9
7
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the input register and the DAC register
are updated with the data contained in the CLR code register—zero, midscale, or full
scale. Default setting clears the output to 0 V.
5
6
4
VOUTE
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
9
11
9
VOUTF
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
6
7
5
VOUTG
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
8
10
8
VOUTH
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
12
14
12
GND
Ground Reference Point for All Circuitry on the Part.
13
15
13
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register
on the falling edge of the serial clock input.
14
16
14
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. Data can be transferred at rates of up to 50 MHz.
EPAD
EPAD
It is recommended that the exposed paddle be soldered to the ground plane.


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