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ICS830154AMI-08LF Datasheet(PDF) 6 Page - Integrated Device Technology

Part # ICS830154AMI-08LF
Description  Over-Voltage Tolerant 1.5V, 1:4 Fanout Buffer
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS830154AMI-08LF Datasheet(HTML) 6 Page - Integrated Device Technology

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ICS830154AGI-08 REVISION A MARCH 29, 2010
6
©2010 Integrated Device Technology, Inc.
ICS830154I-08 Data Sheet
OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER
Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to FOUT ≤ 150MHz.
NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
Table 5C. AC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C
For NOTES, see Table 5B above.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
160
MHz
tpLH
Propagation Delay
(low to high transition); NOTE 1
0.8
1.7
ns
tpHL
Propagation Delay
(high to low transition); NOTE 1
0.8
1.7
ns
tPLZ, tPHZ
Disable Time
(active to high-impedance)
10
ns
tPZL, tPZH
Enable Time
(high-impedance to disable)
10
ns
tsk(o)
Output Skew; NOTE 2, 3
250
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
800
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.076
ps
tR / tF
Output Rise/Fall Time
10% to 90%
0.35
1.2
ns
odc
Output Duty Cycle
48
52
%
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
160
MHz
tpLH
Propagation Delay
(low to high transition); NOTE 1
1.1
2.1
ns
tpHL
Propagation Delay
(high to low transition); NOTE 1
1.1
2.1
ns
tPLZ, tPHZ
Disable Time
(active to high-impedance)
10
ns
tPZL, tPZH
Enable Time
(high-impedance to disable)
10
ns
tsk(o)
Output Skew; NOTE 2, 3
250
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
800
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.193
ps
tR / tF
Output Rise/Fall Time
0.63V to 1.17V
0.12
0.6
ns
odc
Output Duty Cycle
47
53
%


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