ICS871002I-02 Data Sheet

PCI EXPRESS™ JITTER ATTENUATOR

ICS871002AGI-02 REVISION A APRIL 14, 2010

2

©2010 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 20

nQ0, nQ0

Output

Differential output pair. HCSL interface levels.

2

IREF

Input

A fixed precision resistor (475

current used for differential current-mode Qx/nQx clock outputs.

3,

4

FB_OUT,

nFB_OUT

Output

Differential feedback output pair. HCSL interface levels.

5

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs (Qx, FB_OUT) to go low and the inverted outputs (nQx,

nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are

enabled. LVCMOS/LVTTL interface levels.

6

BW_SEL

Input

Pulldown

PLL Bandwidth select input. 0 = 350kHz, 1 = 2200kHz. See Table 3B.

7,

9

F_SEL1,

F_SEL0

Input

Pullup

Pulldown

Frequency select pins. See Table 3C. LVCMOS/LVTTL interface levels

Power

Analog supply pin.

10, 19

Power

Core supply pins.

11

OE

Input

Pullup

Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are

in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A.

12

CLK

Input

Pulldown

Non-inverting differential clock input.

13

nCLK

Input

Pullup

Inverting differential clock input.

14

GND

Power

Power supply ground.

15

FB_IN

Input

Pulldown

Non-inverting differential feedback clock input.

16

nFB_IN

Input

Pullup

Inverting differential feedback clock input.

17, 18

nQ1, Q1

Output

Differential output pair. HCSL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Input Pullup Resistor

51

k

Ω

51

k

Ω