MT41J128M16 datasheet(11/211 Pages) MICRON

Part #	MT41J128M16

Description	DDR3 SDRAM MT41J512M4 ??64 Meg x 4 x 8 Banks MT41J256M8 ??32 Meg x 8 x 8 Banks MT41J128M16 ??16 Meg x 16 x 8 Banks

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit

WRITE = WR, WRS4, WRS8

WRITE AP = WRAP, WRAPS4, WRAPS8

ZQCL = ZQ LONG CALIBRATION

ZQCS = ZQ SHORT CALIBRATION

Bank

active

Reading

Writing

Activating

Refreshing

Self

refresh

Idle

Active

power-

down

ZQ

calibration

From any

state

Power

applied

Reset

procedure

Power

on

Initial-

ization

MRS, MPR,

write

leveling

Precharge

power-

down

Writing

Reading

Automatic

sequence

Command

sequence

Precharging

READ

READ AP

PRE, PREA

WRITE

CKE L

WRITE

WRITE AP

PDE

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE

MPR = Multipurpose register

MRS = Mode register set

PDE = Power-down entry

PDX = Power-down exit

PRE = PRECHARGE

PREA = PRECHARGE ALL

READ = RD, RDS4, RDS8

READ AP = RDAP, RDAPS4, RDAPS8

REF = REFRESH

RESET = START RESET PROCEDURE

SRE = Self refresh entry

2Gb: x4, x8, x16 DDR3 SDRAM

State Diagram

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

11

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MT41J128M16 Datasheet(PDF) 11 Page - Micron Technology

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