Electronic Components Datasheet Search |
|
MT41J256M8 Datasheet(PDF) 7 Page - Micron Technology |
|
MT41J256M8 Datasheet(HTML) 7 Page - Micron Technology |
7 / 211 page Figure 51: Mode Register 0 (MR0) Definitions ................................................................................................ 135 Figure 52: READ Latency .............................................................................................................................. 137 Figure 53: Mode Register 1 (MR1) Definition ................................................................................................. 138 Figure 54: READ Latency (AL = 5, CL = 6) ....................................................................................................... 141 Figure 55: Mode Register 2 (MR2) Definition ................................................................................................. 142 Figure 56: CAS WRITE Latency ...................................................................................................................... 143 Figure 57: Mode Register 3 (MR3) Definition ................................................................................................. 145 Figure 58: MPR Block Diagram ...................................................................................................................... 146 Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 148 Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 149 Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 150 Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 151 Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 153 Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 154 Figure 65: Example: tFAW ............................................................................................................................. 155 Figure 66: READ Latency .............................................................................................................................. 156 Figure 67: Consecutive READ Bursts (BL8) .................................................................................................... 158 Figure 68: Consecutive READ Bursts (BC4) .................................................................................................... 158 Figure 69: Nonconsecutive READ Bursts ....................................................................................................... 159 Figure 70: READ (BL8) to WRITE (BL8) .......................................................................................................... 159 Figure 71: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 160 Figure 72: READ to PRECHARGE (BL8) .......................................................................................................... 160 Figure 73: READ to PRECHARGE (BC4) ......................................................................................................... 161 Figure 74: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 161 Figure 75: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 161 Figure 76: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 163 Figure 77: Data Strobe Timing – READs ......................................................................................................... 164 Figure 78: Method for Calculating tLZ and tHZ ............................................................................................... 165 Figure 79: tRPRE Timing ............................................................................................................................... 165 Figure 80: tRPST Timing ............................................................................................................................... 166 Figure 81: tWPRE Timing .............................................................................................................................. 168 Figure 82: tWPST Timing .............................................................................................................................. 168 Figure 83: WRITE Burst ................................................................................................................................ 169 Figure 84: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 170 Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 170 Figure 86: Nonconsecutive WRITE to WRITE ................................................................................................. 171 Figure 87: WRITE (BL8) to READ (BL8) .......................................................................................................... 171 Figure 88: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 172 Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 173 Figure 90: WRITE (BL8) to PRECHARGE ........................................................................................................ 174 Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 174 Figure 92: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 175 Figure 93: Data Input Timing ........................................................................................................................ 176 Figure 94: Self Refresh Entry/Exit Timing ...................................................................................................... 178 Figure 95: Active Power-Down Entry and Exit ................................................................................................ 182 Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 183 Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 183 Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 184 Figure 99: Power-Down Entry After WRITE .................................................................................................... 184 Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 185 Figure 101: REFRESH to Power-Down Entry .................................................................................................. 185 Figure 102: ACTIVATE to Power-Down Entry ................................................................................................. 186 2Gb: x4, x8, x16 DDR3 SDRAM Features PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. |
Similar Part No. - MT41J256M8 |
|
Similar Description - MT41J256M8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |