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MT41J64M16 Datasheet(PDF) 9 Page - Micron Technology |
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MT41J64M16 Datasheet(HTML) 9 Page - Micron Technology |
9 / 214 page Figure 51: MRS to MRS Command Timing (tMRD) ......................................................................................... 136 Figure 52: MRS to nonMRS Command Timing (tMOD) .................................................................................. 137 Figure 53: Mode Register 0 (MR0) Definitions ................................................................................................ 138 Figure 54: READ Latency .............................................................................................................................. 140 Figure 55: Mode Register 1 (MR1) Definition ................................................................................................. 141 Figure 56: READ Latency (AL = 5, CL = 6) ....................................................................................................... 144 Figure 57: Mode Register 2 (MR2) Definition ................................................................................................. 145 Figure 58: CAS Write Latency ........................................................................................................................ 145 Figure 59: Mode Register 3 (MR3) Definition ................................................................................................. 147 Figure 60: Multipurpose Register (MPR) Block Diagram ................................................................................. 148 Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 151 Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 152 Figure 63: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 153 Figure 64: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 154 Figure 65: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 156 Figure 66: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 157 Figure 67: Example: tFAW ............................................................................................................................. 158 Figure 68: READ Latency .............................................................................................................................. 159 Figure 69: Consecutive READ Bursts (BL8) .................................................................................................... 161 Figure 70: Consecutive READ Bursts (BC4) .................................................................................................... 161 Figure 71: Nonconsecutive READ Bursts ....................................................................................................... 162 Figure 72: READ (BL8) to WRITE (BL8) .......................................................................................................... 162 Figure 73: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 163 Figure 74: READ to PRECHARGE (BL8) .......................................................................................................... 163 Figure 75: READ to PRECHARGE (BC4) ......................................................................................................... 164 Figure 76: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 164 Figure 77: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 164 Figure 78: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 166 Figure 79: Data Strobe Timing – READs ......................................................................................................... 167 Figure 80: Method for Calculating tLZ and tHZ ............................................................................................... 168 Figure 81: tRPRE Timing ............................................................................................................................... 168 Figure 82: tRPST Timing ............................................................................................................................... 169 Figure 83: tWPRE Timing .............................................................................................................................. 171 Figure 84: tWPST Timing .............................................................................................................................. 171 Figure 85: WRITE Burst ................................................................................................................................ 172 Figure 86: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 173 Figure 87: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 173 Figure 88: Nonconsecutive WRITE to WRITE ................................................................................................. 174 Figure 89: WRITE (BL8) to READ (BL8) .......................................................................................................... 174 Figure 90: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 175 Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 176 Figure 92: WRITE (BL8) to PRECHARGE ........................................................................................................ 177 Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 177 Figure 94: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 178 Figure 95: Data Input Timing ........................................................................................................................ 179 Figure 96: Self Refresh Entry/Exit Timing ...................................................................................................... 181 Figure 97: Active Power-Down Entry and Exit ................................................................................................ 185 Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 186 Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 186 Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ........................................... 187 Figure 101: Power-Down Entry After WRITE .................................................................................................. 187 Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 188 1Gb: x4, x8, x16 DDR3 SDRAM Features PDF: 09005aef826aa906 1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. |
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