MT47H512M4 datasheet(5/134 Pages) MICRON

Part #	MT47H512M4

Description	DDR2 SDRAM MT47H512M4 ??64 Meg x 4 x 8 banks MT47H256M8 ??32 Meg x 8 x 8 banks MT47H128M16 ??16 Meg x 16 x 8 banks

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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5 / 134 page

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 2

Table 2: Addressing ......................................................................................................................................... 2

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16

Table 4: Input Capacitance ............................................................................................................................ 22

Table 5: Absolute Maximum DC Ratings ......................................................................................................... 23

Table 6: Temperature Limits .......................................................................................................................... 24

Table 7: Thermal Impedance ......................................................................................................................... 25

Table 8: General IDD Parameters ..................................................................................................................... 26

Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 27

Table 10: DDR2 IDD Specifications and Conditions (Die Revision A) ................................................................. 28

Table 11: DDR2 IDD Specifications and Conditions (Die Revision C) ................................................................ 30

Table 12: AC Operating Specifications and Conditions .................................................................................... 32

Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 44

Table 14: ODT DC Electrical Characteristics ................................................................................................... 45

Table 15: Input DC Logic Levels ..................................................................................................................... 46

Table 16: Input AC Logic Levels ...................................................................................................................... 46

Table 17: Differential Input Logic Levels ......................................................................................................... 47

Table 18: Differential AC Output Parameters ................................................................................................... 49

Table 19: Output DC Current Drive ................................................................................................................ 49

Table 20: Output Characteristics .................................................................................................................... 50

Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 51

Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 52

Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 53

Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 54

Table 25: Input Clamp Characteristics ............................................................................................................ 55

Table 26: Address and Control Balls ................................................................................................................ 56

Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 56

Table 28: AC Input Test Conditions ................................................................................................................ 56

Table 29: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) .................................................... 59

Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) ........................................... 60

Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ...................................................... 63

Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................. 64

Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb ................................................... 65

Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ...................................... 65

Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ...................................... 66

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ...................................... 66

Table 37: Truth Table – DDR2 Commands ...................................................................................................... 71

Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 72

Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 74

Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 75

Table 41: Burst Definition .............................................................................................................................. 79

Table 42: READ Using Concurrent Auto Precharge .......................................................................................... 99

Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 105

Table 44: Truth Table – CKE .......................................................................................................................... 120

2Gb: x4, x8, x16 DDR2 SDRAM

Features

PDF: 09005aef824f87b6

2Gb_DDR2.pdf – Rev. H 10/11 EN

5

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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