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CY7C25682KV18-450BZC Datasheet(PDF) 2 Page - Cypress Semiconductor

Part # CY7C25682KV18-450BZC
Description  72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C25682KV18-450BZC Datasheet(HTML) 2 Page - Cypress Semiconductor

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CY7C25682KV18
CY7C25702KV18
Document Number: 001-66483 Rev. *B
Page 2 of 29
Logic Block Diagram – CY7C25682KV18
Write
Reg
Write
Reg
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS[1:0]
VREF
18
21
18
LD
Control
R/W
DOFF
18
DQ[17:0]
18
CQ
CQ
QVLD
Logic Block Diagram – CY7C25702KV18
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS[3:0]
VREF
36
20
36
LD
Control
R/W
DOFF
36
DQ[35:0]
36
CQ
CQ
QVLD


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