CY7C1370D-200AXC datasheet(8/31 Pages) CYPRESS

Part #	CY7C1370D-200AXC

Description	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM with NoBL??Architecture

Download	31 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

8 / 31 page

CY7C1370D, CY7C1372D

Document Number: 38-05555 Rev. *N

Page 8 of 31

The data written during the write operation is controlled by BW

(BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D) signals.

The CY7C1370D/CY7C1372D provides byte write capability that

is described in the Write Cycle Description table. Asserting the

write enable input (WE) with the selected byte write select (BW)

input will selectively write to only the desired bytes. Bytes not

selected during a byte write operation will remain unaltered. A

synchronous self-timed write mechanism has been provided to

simplify the write operations. Byte write capability has been

included in order to greatly simplify read/modify/write

sequences, which can be reduced to simple byte write

operations.

Because the CY7C1370D and CY7C1372D are common I/O

devices, data should not be driven into the device while the

outputs are active. The output enable (OE) can be deasserted

HIGH before presenting data to the DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for

CY7C1372D) inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for

CY7C1370D

and

DQa,b/DQPa,b for CY7C1372D) are

automatically tristated during the data portion of a write cycle,

regardless of the state of OE.

Burst Write Accesses

The CY7C1370D/CY7C1372D has an on-chip burst counter that

allows the user the ability to supply a single address and conduct

up to four write operations without reasserting the address

inputs. ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Accesses section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the chip enables (CE1, CE2, and CE3) and WE inputs are

ignored and the burst counter is incremented. The correct BW

(BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D) inputs

must be driven in each cycle of the burst write in order to write

the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ

 VDD 0.2 V

–

80

mA

tZZS

Device operation to ZZ

ZZ

 VDD  0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ

 0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current This parameter is sampled

0

–

ns

Similar Part No. - CY7C1370D-200AXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1370D-200AXC	344Kb / 30P	18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
	CY7C1370D-200AXC	511Kb / 28P	18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370D-200AXC	1Mb / 33P	18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM with NoBL Architecture

More results

Similar Description - CY7C1370D-200AXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1370DV25	774Kb / 30P	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1380D	1Mb / 33P	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
	CY7C1380DV33	1Mb / 33P	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
	CY7C1354CV25	835Kb / 33P	9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1354C	1Mb / 32P	9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1371D	1Mb / 37P	18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1380S	1Mb / 31P	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
	CY7C1460BV25	721Kb / 30P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1460AV33	1,000Kb / 31P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370KV25	2Mb / 30P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture

More results

CY7C1370D-200AXC Datasheet(PDF) 8 Page - Cypress Semiconductor

CY7C1370D-200AXC Datasheet(HTML) 8 Page - Cypress Semiconductor

Similar Part No. - CY7C1370D-200AXC

Similar Description - CY7C1370D-200AXC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL