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2N5064RLRAG Datasheet(PDF) 1 Page - ON Semiconductor |
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2N5064RLRAG Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2011 September, 2011 − Rev. 10 1 Publication Order Number: 2N5060/D 2N5060 Series Sensitive Gate Silicon Controlled Rectifiers Reverse Blocking Thyristors Annular PNPN devices designed for high volume consumer applications such as relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and sensing and detection circuits. Supplied in an inexpensive plastic TO−92/TO-226AA package which is readily adaptable for use in automatic insertion equipment. Features • Sensitive Gate Trigger Current − 200 mA Maximum • Low Reverse and Forward Blocking Current − 50 mA Maximum, TC = 110°C • Low Holding Current − 5 mA Maximum • Passivated Surface for Reliability and Uniformity • These are Pb−Free Devices MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Peak Repetitive Off−State Voltage (Note 1) (TJ = *40 to 110°C, Sine Wave, 50 to 60 Hz, RGK = 1 kW) 2N5060 2N5061 2N5062 2N5064 VDRM, VRRM 30 60 100 200 V On-State Current RMS (180° Conduction Angles; TC = 80°C) IT(RMS) 0.8 A *Average On-State Current (180° Conduction Angles) (TC = 67°C) (TC = 102°C) IT(AV) 0.51 0.255 A *Peak Non-repetitive Surge Current, TA = 25°C (1/2 cycle, Sine Wave, 60 Hz) ITSM 10 A Circuit Fusing Considerations (t = 8.3 ms) I2t 0.4 A2s *Average On-State Current (180° Conduction Angles) (TC = 67°C) (TC = 102°C) IT(AV) 0.51 0.255 A *Forward Peak Gate Power (Pulse Width v 1.0 msec; TA = 25°C) PGM 0.1 W *Forward Average Gate Power (TA = 25°C, t = 8.3 ms) PG(AV) 0.01 W *Forward Peak Gate Current (Pulse Width v 1.0 msec; TA = 25°C) IGM 1.0 A *Reverse Peak Gate Voltage (Pulse Width v 1.0 msec; TA = 25°C) VRGM 5.0 V *Operating Junction Temperature Range TJ −40 to +110 °C *Storage Temperature Range Tstg −40 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *Indicates JEDEC Registered Data. SILICON CONTROLLED RECTIFIERS 0.8 A RMS, 30 − 200 V K G A See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ORDERING INFORMATION TO−92 CASE 29 STYLE 10 50xx Specific Device Code Y = Year WW = Work Week MARKING DIAGRAM 2N 50xx YWW PIN ASSIGNMENT 1 2 3 Gate Anode Cathode http://onsemi.com 1 2 3 |
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