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TLK106 Datasheet(PDF) 5 Page - Texas Instruments |
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TLK106 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 99 page  TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 This document describes signals that take on different names depending on configuration. In such cases, the different names are placed together and separated by slash (/) characters. For example, "RXD_3 / PHYAD4". Active low signals are represented by overbars. 2.2 Serial Management Interface (SMI) PIN TYPE DESCRIPTION NAME NO. MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The MDC 20 I maximum MDC rate is 25MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the TX_CLK or the RX_CLK. MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local MDIO 19 I/O controller or the TLK10x may drive the MDIO signal. This pin requires a pull-up resistor with value 2.2k Ω. 2.3 MAC Data Interface PIN TYPE DESCRIPTION NAME NO. MII TRANSMIT CLOCK: MII Transmit Clock provides the 25MHz or 2.5MHz reference clock depending on the speed. Note that in MII mode, this clock has constant phase referenced to TX_CLK 2 O, PD REF_CLK. Applications requiring such constant phase may use this feature. Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and receive. TRANSMIT ENABLE: TX_EN is presented on the rising edge of the TX_CLK . TX_EN TX_EN 3 I, PD indicates the presence of valid data inputs on TXD[3:0] in MII mode, and on TXD [1:0] in the RMII mode. TX_EN is an active high signal. TXD_0 4 TRANSMIT DATA: In MII mode, the transmit data nibble received from the MAC is TXD_1 5 I, PD synchronous to the rising edge of the TX_CLK signal. In RMII mode, TXD [1:0] received from TXD_2 6 the MAC is synchronous to the 50MHz reference clock on XI. TXD_3 7 RECEIVE CLOCK: In MII mode it is the receive clock that provides either a 25MHz or 2.5MHz RX_CLK 25 O reference clock, depending on the speed, that is derived from the received data stream. RECEIVE DATA VALID: This pin indicates valid data is present on the RXD [3:0] for MII mode RX_DV / MII_MODE 26 S, O, PD or on RXD [1:0] for RMII mode, independently from Carrier Sense. RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to RX_ER / AMDIX_EN 28 S, O, PU RX_CLK and in RMII mode, synchronously to XI (50MHz). This pin is not required to be used by the MAC, in either MII or RMII, because the PHY is corrupting data on a receive error. RECEIVE DATA: Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK. They contain valid data when RX_DV is asserted. A nibble RXD [3:0] RXD_0 / PHYAD1 30 is received in the MII mode and 2-bits RXD[1:0] is received in the RMII Mode. RXD_1 / PHYAD2 31 S, O, PD RXD_2 / PHYAD3 32 PHY address pins PHYAD[4:1] are multiplexed with RXD [3:0], and are pulled down. PHYAD0 RXD_3 / PHYAD4 1 (LSB of the address) is multiplexed with COL on pin 29, and is pulled up. If no external pullup/pulldown is present, the default address is 0x01. CARRIER SENSE: In MII mode this pin is asserted high when the receive medium is non-idle. CRS / CRS_DV/ 27 S, O, PU LED_CFG CARRIER SENSE/RECEIVE DATA VALID: In RMII mode, this pin combines the RMII Carrier and Receive Data Valid indications. COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10Base- COL / PHYAD0 29 S, O, PU T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and receive media are non-idle. This pin is not used in RMII mode. Copyright © 2012–2013, Texas Instruments Incorporated Pin Descriptions 5 Submit Documentation Feedback Product Folder Links: TLK105 TLK106 |
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