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TLK105 Datasheet(PDF) 11 Page - Texas Instruments |
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TLK105 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 99 page  2.2 kW VCC PHYAD4 = 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1 TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 3.6 MII Isolate Mode The TLK10x can be put into MII-Isolate mode by writing bit 10 of the BMCR register. When in the MII-Isolate mode, the TLK10x ignores packet data present at the TXD[3:0], TX_EN inputs, and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in isolate mode, the TLK10x continues to respond to all management transactions. When in isolate mode, the PMD output pair does not transmit packet data, but continues to source 100Base-TX scrambled idles or 10Base-T normal link pulses. The TLK10x can auto-negotiate or parallel detect on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the TLK10x is in Isolate mode. 3.7 PHY Address The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 3-2. Table 3-2. PHY Address Mapping PIN Number PHYAD FUNCTION RXD FUNCTION 29 PHYAD0 COL 30 PHYAD1 RXD_0 31 PHYAD2 RXD_1 32 PHYAD3 RXD_2 1 PHYAD4 RXD_3 Each TLK10x or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK10x can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address is 00001 (0x01h). See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the PHYAD configuration results in address 00011 (0x03h). Figure 3-3. Illustrative PHYAD Configuration Example Copyright © 2012–2013, Texas Instruments Incorporated Hardware Configuration 11 Submit Documentation Feedback Product Folder Links: TLK105 TLK106 |
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