10 PF

Enable

See Table

0.022 PF

See Table

0.022 PF

See Table

100 PF

LMZ12001

5V

5.62k

1.07k

100k

7.5...20V

VOUT RFBT

RFBB

RON

VIN Range

3.3V

3.32k

1.07k

61.9k

6.0...20V

2.5V

2.26k

1.07k

47.5k

5.5...20V

1.8V

1.87k

1.50k

32.4k

4.5...20V

1.5V

1.00k

1.13k

28.0k

4.5...20V

1.2V

4.22k

8.45k

22.6k

4.5...19V

0.8V

0

39.2k

24.9k

4.5...18V

LMZ12001

www.ti.com

SNVS651F – JANUARY 2010 – REVISED MARCH 2013

Simplified Application Schematic

Connection Diagram

Figure 5. 7-Lead PFM

Top View

Pin Descriptions

Pin

Name

Description

1

VIN

Supply input — Nominal operating range is 4.5V to 20V . A small amount of internal capacitance is contained within the

package assembly. Additional external input capacitance is required between this pin and exposed pad.

2

RON

25k to 124k ohms.

3

EN

Enable — Input to the precision enable comparator. Rising threshold is 1.18V nominal; 90 mV hysteresis nominal.

Maximum recommended input level is 6.5V.

4

GND

Ground — Reference point for all stated voltages. Must be externally connected to EP.

5

SS

Soft-Start — An internal 8 µA current source charges an external capacitor to produce the soft-start function. This node is

discharged at 200 µA during disable, over-current, thermal shutdown and internal UVLO conditions.

6

FB

Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation reference

point is 0.8V at this input pin. Connected the feedback resistor divider between the output and ground to set the output

voltage.

7

VOUT

Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad.

EP

EP

Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be

electrically connected to pin 4 external to the package.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2010–2013, Texas Instruments Incorporated

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