TLC59116

www.ti.com

SLDS157D

– FEBRUARY 2008 – REVISED JULY 2011

TIMING REQUIREMENTS

STANDARD MODE

FAST MODE

FAST MODE PLUS

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

0

100

0

400

0

1000

kHz

4.7

1.3

0.5

μs

Start conditions

Hold time (repeated) Start condition

4

0.6

0.26

μs

Setup time for a repeated Start

4.7

0.6

0.26

μs

condition

Setup time for Stop condition

4

0.6

0.26

μs

Data hold time

0

0

0

ns

0.3

3.45

0.1

0.9

0.05

0.45

μs

0.3

3.45

0.1

0.9

0.05

0.45

μs

Data setup time

250

100

50

ns

Low period of SCL clock

4.7

1.3

0.5

μs

High period of SCL clock

4

0.6

0.26

μs

Fall time of both SDA and SCL

(6)

300

120

ns

Rise time of both SDA and SCL

(6)

300

120

ns

signals

Pulse width of spikes that must be

50

50

50

ns

Reset

Reset pulse width

10

10

10

ns

Reset recovery time

0

0

0

ns

400

400

400

ns

(1)

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

low for a minimum of 25 ms. Disable bus time-out feature for dc operation.

(2)

(3)

(4)

bridge the undefined region of the SCL falling edge.

(5)

at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines

(6)

(7)

Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

(8)

Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.

(9)

Copyright

© 2008–2011, Texas Instruments Incorporated

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