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8305AG Datasheet(PDF) 6 Page - Integrated Device Technology |
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8305AG Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 17 page IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 6 ICS8305AG REV. C OCTOBER 23, 2008 ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C All parameters measured at ƒ ≤ 350MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C For NOTES, see Table 5A above. Parameter Symbol Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tpLH Propagation Delay, Low to High LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B 1.75 2.75 ns tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 6 700 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 0.04 ps tR / tF Output Rise/Fall Time; NOTE 4 20% to 80% 100 700 ps odc Output Duty Cycle Ref = CLK/nCLK 45 55 % Ref = LVCMOS_CLK, ƒ ≤ 300MHz 45 55 % tEN Output Enable Time; NOTE 4 5ns tDIS Output Disable Time; NOTE 4 5ns Parameter Symbol Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tpLH Propagation Delay, Low to High LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B 1.8 2.9 ns tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 6 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 0.04 ps tR / tF Output Rise/Fall Time; NOTE 4 20% to 80% 100 700 ps odc Output Duty Cycle Ref = CLK/nCLK 44 56 % Ref = LVCMOS_CLK, ƒ ≤ 300MHz 44 56 % tEN Output Enable Time; NOTE 4 5ns tDIS Output Disable Time; NOTE 4 5ns |
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