ISL80083

2

FN7886.1

May 15, 2013

Pin Configuration

ISL80083

(25 BALL CSP 2.11 x 2.13mm)

TOP VIEW

VIN_HOST

VSELECT

CLK2P3OUT

PHASE

CLK2P3IN

RESET

VOLDO

GNDLDO

SCLK

VIN_REMOTE

OSC_EN

V3CLAMP

GND

UART_EN

CFG2

1VAUX

PGND

CFG2_CR

LSRX_CR

FB

-OSCOUT

SDAT

LSRX

+OSCOUT

OSCGND

A

B

C

D

E

1

23

4

5

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

A1

-OSCOUT

Negative terminal of the precision 33MHz oscillator differential output.

A2

+OSCOUT

Positive terminal of the precision 33MHz oscillator differential output.

A3

OSCGND

Isolated ground for the internal 33MHz oscillator.

A4

CLK2P3IN

2.3V input for the 33MHz oscillator. Connect a 220nF capacitor from CLK2P3OUT to OSCGND.

A5

CLK2P3OUT

2.3V internal LDO output for the 33MHz oscillator. Connect CLK2P3IN to CLK2P3OUT along with a 220nF capacitor

for low noise performance.

B1

CFG2

This is the output of the level shifter from the CFG2_CR rail control signal shifting from 1.8V to 3V.

B2

LSRX

This is the output of the level shifter from the LSRX_CR rail control signal shifting from 1.8V to 3V.

B3

UART_EN

Level shift of LSRX logic enable control. The output LSRX is in high Z state when UART_EN is pulled low. There is a

125k

Ω pull-down resistor from this pin to GND.

B4

RESET

This is a totem pole output to indicate a fault mode. The output is low if any of the fault is detected. The output is high

during normal operation.

B5

V3CLAMP

This rail is a 3V LDO sourcing from VSELECT.

C1

CFG2_CR

This is the input to the level shifter for the CONFIG2 rail control signal shifting from 3V to 1.8V.

C2

LSRX_CR

This is the input to the level shifter from the LSRX rail control signal.

C3

VOLDO

Output of the LDO.