LMX2581

SNAS601D – AUGUST 2012 – REVISED APRIL 2013

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Functional Description

The LMX2581 is a low power, high performance frequency synthesizer system which includes a PLL (Phased

Locked Loop), VCO (Voltage Controlled Oscillator), VCO Divider, and Programmable Output Buffer.

OSCin INPUT and OSCin DOUBLER

The OSCin pin is driven with a single-ended signal which is used to as a frequency reference. Before the OSCin

frequency reaches the phase detector, it can be doubled with the OSCin doubler and/or divided with the PLL R

divider.

Because the OSCin signal is used as a clock for the VCO calibration, the OSC_FREQ field needs to be

programmed correctly and a proper signal needs to be applied at the OSCin pin at the time of programming the

R0 register order for the VCO calibration to properly work. Higher slew rates tend to yield the best fractional

spurs and phase noise, so a square wave signal is best for OSCin. If using a sine wave, higher frequencies tend

to yield better phase noise and fractional spurs due to their higher slew rates. The OSCin pin his high

impedance, so for optimal performance, it is recommended to use either a shunt resistor or resistive pad to make

such that the impedances looking towards our device and from the looking away from our device (as seen by the

OSCin pin) are both close to 50 ohms

R DIVIDER

The R divider divides the OSCin frequency down to the phase detector frequency. With this device, it is possible

to use both the doubler and the R divider at the same time.

PLL N DIVIDER AND FRACTIONAL CIRCUITRY

The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to

4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the fractional portion,

PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are software programmable.

So in general, the total N divider value, N, is determined by: N = PLL_N + PLL_NUM / PLL_DEN The order of

the delta sigma modulator is programmable from integer mode to third order. There are also several dithering

modes that are also programmable. In order to make the fractional spurs consistent, the modulator is reset any

time that the R0 register is programmed.

PLL PHASE DETECTOR AND CHARGE PUMP

The phase detector compares the outputs of the R and N dividers and generates a correction current

corresponding to the phase error. This charge pump current is software programmable to many different levels.

outputs a correction current the loop filter, which is implemented with external components.

EXTERNAL LOOP FILTER

The LMX2581 requires an external loop filter. The design of this filter is application specific and can be done by

software provided on the Texas Instruments website. For the LMX2581, it is recommended for the best possible

VCO noise to ensure a capacitor of at least 3.3 nF next to the VCO. Not doing so will degrade the VCO phase

noise at offsets in the 100k-1MHz region, although the device will still function properly.

LOW NOISE, FULLY INTEGRATED VCO

The VCO takes the voltage from the loop filter and converts this into a frequency. The VCO frequency is related

fully integrated, including the tank inductors.

In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the

internal VCO is actually four VCO cores working in conjunction. These cores starting from lowest frequency to

highest frequency are VCO 1, VCO 2, VCO 3, and VCO 4. Each VCO core has 256 different frequency bands.

This creates the need for frequency calibration in order to determine the correct VCO core and correct frequency

band in that VCO core. The frequency calibration routine is activated any time that the R0 register is

programmed with the NO_FCAL bit equal to zero. In order for this frequency calibration to work properly, the

OSC_FREQ field needs to be set to the correct setting. The are also programmable settings that allow the user

to suggest a particular VCO core for the device to choose.

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