CY3670 datasheet(5/13 Pages) CYPRESS

Part #	CY3670

Description	Single-PLL General Purpose EPROM Programmable Clock Generator

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY2907

Document Number: 38-07137 Rev. *G

Page 5 of 13

Electrical Characteristics at 5.0 V Commercial

VDD = 4.5 V to 5.5 V, TA = 0 °C to +70 °C

Parameter

Description

Test Conditions

Min

Max

Unit

VIH

High-level input voltage

Except crystal inputs

2.0

–

V

VIL

Low-level input voltage

Except crystal inputs

–

0.8

V

VOH[6]

High-level output voltage

VDD = VDD Min. IOH = –30 mA

CLKA

2.4

–

V

VOL[6]

Low-level output voltage

VDD = VDD Min. IOL = 10 mA

CLKA

–

0.4

V

IOH[6]

Output high current

VOH = 2.0 V

–

–35

mA

IOL[6]

Output low current

VOL = 0.8 V

22

–

mA

IIH

Input high current

VIH = VDD

–2

2

µA

IIL

Input low current

VIL = 0V

–

20

µA

IDD[7]

Power supply current

PD HIGH, CLKA = 50 MHz

–

42

mA

IDD

Power supply current

PD LOW, Logic inputs LOW

–

100

µA

IDD

Power supply current

PD LOW, Logic inputs HIGH

–

40

µA

RPU[6]

Pull-up resistor

VIN = VDD – 1.0 V

–

700

k



Electrical Characteristics at 3.3 V Commercial

VDD = 3.0 V to 3.6 V, TA = 0 °C to +70 °C

Parameter

Description

Test Conditions

Min

Max

Unit

VIH

High-level input voltage

Except crystal inputs

0.7 × VDD

–

V

VIL

Low-level input voltage

Except crystal inputs

–

0.2 × VDD

V

VOH[8]

High-level output voltage

CLKA, IOH = –5 mA

0.85 × VDD

–

V

VOL[8]

Low-level output voltage

CLKA, IOL = 6 mA

–

0.1 × VDD

V

IOH[8]

Output high current

VOH = 0.7 × VDD

–

–10

mA

IOL[8]

Output low current

VOL = 0.2 × VDD

15

–

mA

IIH

Input high current

VIH = VDD

–2

2

µA

IIL

Input low current

VIL = 0 V

–

10

µA

IDD[9]

Power supply current

PD HIGH, CLKA = 50 MHz

–

40

mA

IDD

Power supply current

PD LOW, Logic inputs LOW

–

40

µA

IDD

Power supply current

PD LOW, Logic inputs HIGH

–

12

µA

RPU[8]

Pull-up resistor

VIN = VDD – 0.5 V

–

900

k



Notes

6. Guaranteed by design, not 100% tested in production.

7. Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:

IDD (mA) = VDD × (6.25 + (0.055 × FREF) + (0.0017 × CLOAD × (FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz.

8. Guaranteed by design, not 100% tested in production.

9. Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:

IDD (mA) = VDD × (6.25 + (0.055 × FREF) + (0.0017 × CLOAD × (FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz.

:

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