CY2907

Document Number: 38-07137 Rev. *G

Page 6 of 13

Switching Characteristics at 5.0 V Commercial[10]

Parameter Output[11]

Description

Test Conditions

Min

Max

Unit

CLKA

Output rise time 0.8 V to 2.0 V

15 pF load

–

1.40

ns

CLKA

Output fall time 2.0 V to 0.8 V

15 pF load

–

1.00

ns

CLKA

Output rise time 20% to 80%

15 pF load

–

3.5

ns

CLKA

Output fall time 80% to 20%

15 pF load

–

2.5

ns

CLKA

Duty cycle

15 pF load at 1.4 V

45.0

55.0

%

XTALIN

Input frequency

Crystal oscillator

10

25

MHz

XTALIN

Input frequency

External input clock[12]

1

30

MHz

CLKA

Output frequency

CY2907, 15 pF load

0.5

130.0

MHz

CY2907F, 15 pF load

0.5

100.0

MHz

CLKA

Jitter (one sigma)

20 MHz to 130 MHz

–

150

ps

CLKA

Jitter (one sigma)

14 MHz to 20 MHz

–

200

ps

CLKA

Jitter (one sigma)

Less than 14 MHz

–

1

%

CLKA

Jitter (absolute)

20 MHz to 130 MHz

–250

+ 250

ps

CLKA

Jitter (absolute)

14 MHz to 20 MHz

–500

+ 500

ps

CLKA

Jitter (absolute)

Less than 14 MHz

–

3

%

Power-up time

–

18

ms

CLKA

Transition time

8 MHz to 66.6 MHz

–

13

ms

Switching Characteristics at 3.3 V Commercial[10]

Parameter Output[11]

Description

Test Conditions

Min

Max

Unit

CLKA

Output rise time 20% to 80%

15 pF Load

–

3.5

ns

CLKA

Output fall time 80% to 20%

15 pF Load

–

2.5

ns

CLKA

Duty cycle

15 pF Load at 1.4 V

40.0

53.0

%

XTALIN

Input frequency

Crystal Oscillator

10

25

MHz

XTALIN

Input frequency

External Input Clock[12]

130

MHz

CLKA

Output frequency

CY2907, 15 pF Load

0.5

100.0

MHz

CY2907F, 15 pF Load

0.5

80.0

MHz

CLKA

Jitter (one sigma)

25 MHz to 100 MHz

–

150

ps

CLKA

Jitter (one sigma)

14 MHz to 25 MHz

–

200

ps

CLKA

Jitter (one sigma)

Less than 14 MHz

–

1

%

CLKA

Jitter (absolute)

25 MHz to 120 MHz

–250

+250

ps

CLKA

Jitter (absolute)

14 MHz to 25 MHz

–500

+500

ps

CLKA

Jitter (absolute)

Less than 14 MHz

–

3

%

Power-up time

–

18

ms

CLKA

Transition time

8 MHz to 66.6 MHz

–

13

ms

Notes

10. Guaranteed by design, not 100% tested in production.

11. REFCLK output can also be configured to be driven by the PLL. In that case these characteristics are also valid.

12. Refer to the application note Crystal Oscillator Topics when using an external reference clock as an input frequency source.