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ADS42JB49IRGCT Datasheet(PDF) 9 Page - Texas Instruments |
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ADS42JB49IRGCT Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 70 page  CLKIN SYNC~ t SU_SYNC~ Sample N t H_SYNC~ CLKIN SYSREF t SU_SYSREF Sample N t H_SYSREF Input Clock CLKINM CLKINP SYNC~ t H_SYNC~ t SU_SYNC~ SYNC~ Deasserted Latency t D K28.5 ILA Sequence Dx0P, Dx0M (1) Dx1P, Dx1M (1) K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.0 K28.0 K28.0 K28.0 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TIMING DIAGRAMS (continued) (1) x = A for channel A and B for channel B. Figure 3. SYNC~ Latency in ILAS Phase (Two-Lane Mode) Figure 4. SYSREF Timing (Subclass 1) Figure 5. SYNC~ Timing (Subclass 2) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADS42JB49 ADS42JB69 |
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