- 8 -

K4H561638N

datasheet

DDR SDRAM

Rev. 1.01

K4H560838N

K4H560438N

7. Input/Output Function Description

SYMBOL

TYPE

DESCRIPTION

CK, CK

Input

Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the

positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Inter-

nal clock signals are derived from CK/CK.

CKE

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buf-

fers and output drivers. Taking CKE Low provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for

POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH

exit, and for output disable. CKE must be maintained high throughput READ and WRITE accesses. Input

buffers, excluding CK, CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are

sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH

CS

Input

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All com-

mands are masked when CS is registered HIGH. CS provides for external bank selection on systems with

multiple banks. CS is considered part of the command code.

RAS, CAS, WE

Input

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

LDM,(UDM)

Input

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although

DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds

to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or

floating during READs.

BA0, BA1

Input

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE

command is being applied.

A [0 : 12]

Input

Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE

applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is

selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET com-

mand. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

DQ

I/O

Data Input/Output : Data bus

LDQS,(U)DQS

I/O

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write

data. Used to capture write data. For the x16, LDQS corresponds to the data on

DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15.

LDQS is NC on x4 and x8.

NC

-

No Connect : No internal electrical connection is present.

Supply

DQ Power Supply : +2.5V ± 0.2V.

Supply

DQ Ground.

Supply

Power Supply : +2.5V ± 0.2V.

Supply

Ground.

Input

SSTL_2 reference voltage.