TLV5624

2.7V TO 5.5V LOW POWER 8BIT DIGITALTOANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS235B − JULY 1999 − REVISED APRIL 2004

10

WWW.TI.COM

TYPICAL CHARACTERISTICS

Figure 12

−0.50

−0.25

0.00

0.25

0.50

0

32

64

96

128

160

192

224

256

Digital Output Code

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

APPLICATION INFORMATION

general function

The TLV5624 is an 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial

interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a

rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

2REF

CODE

2n

[V]

n = 8 (bits). The 16-bit word, consisting of control bits and a new DAC value, is illustrated in the data format

section. A power on reset initially resets the internal latches to a defined state (all bits zero).

serial interface

The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting

with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or

FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new

level.

The serial interface of the TLV5624 can be used in two basic modes:

Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of

the data source (DSP or microcontroller). Figure 13 shows an example with two TLV5624s connected directly

to a TMS320 DSP.