Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

t

RCP

Receiver out Clock

Period

Figure 3

t

RCLK

25

62.5

ns

t

CLH

CMOS/TTL Low-to-High

Transition Time

CL=15pF

Figure 2

Rout(0-9),

1.2

4

ns

t

CHL

CMOS/TTL High-to-Low

Transition Time

LOCK, RCLK

1.1

4

ns

t

DD

Deserializer Delay

Figure 4

All Temp./All Freq. 1.75*t

1.75*t

1.75*t

ns

Room Temp

3.3V/40MHz

1.75*t

1.75*t

1.75*t

t

ROS

ROUT (0-9) Setup Data to

RCLK

Figure 5

RCLK

0.4*t

RCP

0.5*t

RCP

ns

t

ROH

ROUT (0-9) Hold Data to

RCLK

−0.4*t

RCP

−0.5*t

RCP

ns

t

RDC

RCLK Duty Cycle

45

50

55

%

t

HZR

HIGH to TRI-STATE Delay

Figure 6

Rout(0-9),

LOCK

4.2+0.5*t

RCP

10+t

RCP

ns

t

LZR

LOW to TRI-STATE Delay

4.5+0.5*t

RCP

10+t

RCP

ns

t

ZHR

TRI-STATE to HIGH Delay

6+0.5*t

RCP

12+t

RCP

ns

t

ZLR

TRI-STATE to LOW Delay

6.0+0.5*t

RCP

12+t

RCP

ns

t

DSR1

Deserializer PLL Lock Time

from PWRDWN (with

SYNCPAT)

Figure 7

Figure 8

(Note 4)

16MHz

410

µs

40MHz

1.31

3

µs

t

DSR2

Deserializer PLL Lock time

from SYNCPAT

16MHz

1.2

5

µs

40MHz

0.47

1

µs

t

ZHLK

TRI-STATE to HIGH Delay

(Power-up)

LOCK

4.62

12

ns

t

RNM

Deserializer Noise Margin

Figure 9

(Note 5)

16 MHz

900

1100

ps

40 MHz

450

730

ps

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,

∆VOD, VTH

and VTL which are differential voltages.

Note 4: For the purpose of specifying Deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions

of the incoming data stream (SYNCPATs). It is recommended that the Deserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time required

for the Deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before initiating

either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled Deserializer when the input (RI+ and RI-) conditions change from not

receiving data to receiving synchronization patterns (SYNCPATs).

Note 5: tRNM is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur.

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