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ATSAM3N00AA-MU Datasheet(PDF) 7 Page - ATMEL Corporation |
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ATSAM3N00AA-MU Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 60 page  7 11011BS–ATARM–22-Feb-12 SAM3N Summary 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator, ADC and DAC Power Supply Power 1.8V to 3.6V(3) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.65 V to 1.95V VDDCORE Power the core, the embedded memories and the peripherals Power 1.65V to 1.95V Connected externally to VDDOUT GND Ground Ground Clocks, Oscillators and PLLs XIN Main Oscillator Input Input VDDIO Reset State: - PIO Input - Internal Pull-up disabled - Schmitt Trigger enabled(1) XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output PCK0 - PCK2 Programmable Clock Output Output Reset State: - PIO Input - Internal Pull-up enabled - Schmitt Trigger enabled(1) ICE and JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input VDDIO Reset State: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled(1) TDI Test Data In Input TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output TMS/SWDIO Test Mode Select /Serial Wire Input/Output Input / I/O JTAGSEL JTAG Selection Input High Permanent Internal pull-down |
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