4

3308J–FLASH–4/05

AT49BV322A(T)

3.

Block Diagram

4.

Device Operation

4.1

Read

The AT49BV322A(T) is accessed like an EPROM. When CE and OE are low and WE is high,

the data stored at the memory location determined by the address pins are asserted on the out-

puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus contention.

4.2

Command Sequences

When the device is first powered on, it will be reset to the read or standby mode, depending

upon the state of the control line inputs. In order to perform other device functions, a series of

command sequences are entered into the device. The command sequences are shown in the

“Command Definition Table” on page 13 (I/O8 - I/O15 are don’t care inputs for the command

codes). The command sequences are written by applying a low pulse on the WE or CE input

with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE

or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard

IDENTIFIER

REGISTER

STATUS

REGISTER

DATA

COMPARATOR

OUTPUT

BUFFER

INPUT

BUFFER

COMMAND

REGISTER

Y-GATING

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

CE

WE

OE

RESET

BYTE

RDY/BUSY

VPP

VCC

GND

Y-DECODER

X-DECODER

INPUT

BUFFER

ADDRESS

LATCH

I/O0 - I/O15/A-1

A0 - A20

MAIN

MEMORY