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MPC8248VRPIEA Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MPC8248VRPIEA Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 61 page MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Overview This figure shows the block diagram of the SoC. Figure 1. SoC Block Diagram 1.1 Features The major features of the SoC are as follows: • Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 266–400 MHz — Separate 16 KB data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — Power Architecture®-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — Supports bus snooping for cache coherency 16 KB G2_LE Core I-Cache I-MMU 16 KB D-Cache D-MMU Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM Serial DMA 60x-to-PCI Bridge Memory Controller Clock Counter System Functions System Interface Unit (SIU) PCI Bus 32 bits, up to 66 MHz FCC1 FCC2 SCC1 SCC3 SCC4 SMC1 SMC2 SPI I2C Serial Interface 2 MII/RMII Port Ports 60x Bus Interrupt Controller Time Slot Assigner 2 TDM Ports Non-Multiplexed I/O Bus Interface Unit Virtual IDMAs 16 KB Security (SEC)1 2 1 8-bit Utopia Serial interface 4 KB Instruction RAM Data RAM Notes: 1 MPC8272/8248 only 2 MPC8272/8271 only USB 2.0 |
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