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FM31L278 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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FM31L278 Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 30 page  FM33256B SPI Companion w/ FRAM Document Number: 001-86213 Rev. ** Page 5 of 30 Figure 2. Low VDD Reset A watchdog timer can also be used to drive an active reset signal. The watchdog is a free-running programmable timer. The timeout period can be software programmed from 60 ms to 1.8 seconds in 60 ms increments via a 5-bit nonvolatile setting (register 0Ch). Figure 3. Watchdog Timer The watchdog also incorporates a window timer feature that allows a delayed start. The starting time and ending time defines the window and each may be set independently. The starting time has 25 ms resolution and 0 ms to 775 ms range. Figure 4. Window Timer The watchdog EndTime value is located in register 0Ch, bits 4-0, the watchdog enable is bit 7. The watchdog is restarted by writing the pattern 1010b to the lower nibble of register 0Ah. Writing the correct pattern will also cause the timer to load new timeout values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is free- running. Prior to enabling it, users should restart the timer as described above. This assures that the full timeout is provided immediately after enabling. The watchdog is disabled when VDD drops below VTP. Note setting the EndTime timeout setting to all zeroes (00000b) disables the timer to save power. The listing below summarizes the watchdog bits. Watchdog StartTime WDST4-0 0Bh, bits 4-0 Watchdog EndTime WDET4-0 0Ch, bits 4-0 Watchdog Enable WDE 0Ch, bit 7 Watchdog Restart WR3-0 0Ah, bits 3-0 Watchdog Flags EWDF, 09h, bit 7 LWDF 09h, bit 6 The programmed StartTime value is a guaranteed maximum time while the EndTime value is a guaranteed minimum time, and both vary with temperature and VDD voltage. The watchdog has two additional controls associated with its operation. The nonvolatile enable bit WDE allows the /RST to go active if the watchdog reaches the timeout without being restarted. If a reset occurs, the timer will restart on the rising edge of the reset pulse. If WDE is not enabled, the watchdog timer still runs but has no effect on /RST. The second control is a nibble that restarts the timer, thus preventing a reset. The timer should be restarted after changing the timeout value. This procedure must be followed to properly load the watchdog registers: Address 1. Write the StartTime value 0Bh 2. Write the EndTime value and WDE=1 0Ch 3. Issue a Restart command 0Ah The restart command in step 3 must be issued before tDOG2, which was programmed in step 2. The window timer starts counting when the restart command is issued. Manual Reset The /RST is a bi-directional signal allowing the FM33256B to filter and de-bounce a manual reset switch. The /RST input detects an external low condition and responds by driving the /RST signal low for 100 ms (max.). This effectively filters and de- bounces a reset switch. After this timeout (tRPU), the user may continue pulling down on the /RST pin, but SPI commands will not be locked out. RST Watchdog Restart Start Time End Time 100 ms (max) Window Timebase Down Counter Watchdog Timer Settings 100 ms clock WDE /RST WR3-0 = 1010b to restart VDD VTP tRPU RST |
Similar Part No. - FM31L278 |
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Similar Description - FM31L278 |
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