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FM28V102 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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FM28V102 Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 16 page  FM28V102 - 64Kx16 F-RAM Document Number: 001-86601 Rev. ** Page 9 of 16 Read Cycle AC Parameters (TA = -40 C to + 85 C, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max Units Notes tRC Read Cycle Time 105 - 90 - ns tCE Chip Enable Access Time - 70 - 60 ns tAA Address Access Time - 105 - 90 ns tOH Output Hold Time 20 - 20 - ns tAAP Page Mode Address Access Time - 40 - 30 ns tOHP Page Mode Output Hold Time 3 - 3 - ns tCA Chip Enable Active Time 70 - 60 - ns tPC Precharge Time 35 - 30 - ns tBA /UB, /LB Access Time - 25 - 15 ns tAS Address Setup Time (to /CE low) 0 - 0 - ns tAH Address Hold Time (/CE-controlled) 70 - 60 - ns tOE Output Enable Access Time - 25 - 15 ns tHZ Chip Enable to Output High-Z - 15 - 10 ns 1 tOHZ Output Enable High to Output High-Z - 15 - 10 ns 1 tBHZ /UB, /LB High to Output High-Z - 15 - 10 ns 1 Write Cycle AC Parameters (TA = -40 C to + 85 C, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max Units Notes tWC Write Cycle Time 105 - 90 - ns tCA Chip Enable Active Time 70 - 60 - ns tCW Chip Enable to Write Enable High 70 - 60 - ns tPC Precharge Time 35 - 30 - ns tPWC Page Mode Write Enable Cycle Time 40 - 30 - ns tWP Write Enable Pulse Width 22 - 18 - ns tWP2 /UB, /LB Pulse Width 22 - 18 - ns tWP3 /WE Low to /UB, /LB High 22 - 18 - ns tAS Address Setup Time (to /CE low) 0 - 0 - ns tAH Address Hold Time (/CE-controlled) 70 - 60 - ns tASP Page Mode Address Setup Time (to /WE low) 8 - 5 - ns tAHP Page Mode Address Hold Time (to /WE low) 20 - 15 - ns tWLC Write Enable Low to Chip Disabled 30 - 25 - ns tBLC /UB, /LB Low to Chip Disabled 30 - 25 ns tWLA Write Enable Low to A(15:2) Change 30 - 25 - ns tAWH A(15:2) Change to Write Enable High 105 - 90 - ns tDS Data Input Setup Time 20 - 15 - ns tDH Data Input Hold Time 0 - 0 - ns tWZ Write Enable Low to Output High Z - 10 - 10 ns 1 tWX Write Enable High to Output Driven 8 - 5 - ns 1 tBDS Byte Disable Setup Time (to /WE low) 8 - 5 - ns tBDH Byte Disable Hold Time (to /WE high) 8 - 5 - ns Notes 1. This parameter is characterized but not 100% tested. Capacitance (TA = 25 C , f=1 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CI/O Input/Output Capacitance (DQ) - 8 pF CIN Input Capacitance - 6 pF CZZ Input Capacitance of /ZZ pin - 8 pF |
Similar Part No. - FM28V102 |
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Similar Description - FM28V102 |
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