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CYRF69103-40LFXC Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CYRF69103-40LFXC Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 72 page  CYRF69103 Document Number: 001-07611 Rev *I Page 7 of 72 Functional Block Overview All the blocks that make up the PRoC LP are presented in this section. 2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in eight steps. The supply current of the device is reduced as the RF output power is reduced. Frequency Synthesizer Before transmission or reception may commence, it is necessary for the frequency synthesizer to settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The “fast channels” (<100 s settling time) are every 3rd frequency, starting at 2400 MHz up to and including 2472 MHz (that is, 0,3,6,9…….69 and 72). Baseband and Framer The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, and EOP detection and length field. Data Transmission Modes and Data Rates The SoC supports four different data transmission modes: ■ In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. ■ In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. ■ In DDR mode, 2 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted (as in the CYWUSB6934 DDR mode). ■ In SDR mode, 1 bit is encoded in each DATA_CODE_ADR derived code symbol transmitted (as in the CYWUSB6934 standard modes). 24 P1.2 GPIO 25 P1.3 / nSS Slave Select 26 P1.4 / SCK SPI Clock 27 IRQ Radio Function Interrupt output, configure High, Low or as Radio GPIO. 28 P1.5 / MOSI MOSI pin from microcontroller function to radio function. 29 MISO 3-wire SPI mode configured as Radio GPIO. In 4-wire SPI mode sends data to MCU function. 30 XOUT Buffered CLK, PACTL_n or Radio GPIO. 31 PACTL Control for external PA or Radio GPIO. 32 P1.6 GPIO 33 VIO 1.8 V to 3.6V to main power supply rail for Radio I/O. 34 RST Radio Reset. Connected to pin 40 with 0.47 F. Must have a RST = HIGH event the very first time power is applied to the radio otherwise the state of the radio control registers is unknown. 35 P1.7 GPIO 36 VDD1.8 Regulated logic bypass. Connected to 0.47 F to GND. 37 L/D Inductor/Diode connection for Boost. When Internal PMU is not being used connect L/D to GND. 38 P0.7 GPIO 39 Vbat0 Connected to1.8 V to 3.6 V main power supply, through 0.047 F bypass C. 40 VREG Boost regulator output voltage feedback 41 E-pad Must be connected to ground. 42 Corner Tabs Do Not connect corner tabs. Pin Definitions (continued) Pin Name Description Table 3. Internal PA Output Power Step Table PA Setting Typical Output Power (dBm) 7+4 60 5–5 4–10 3–15 2–20 1–25 0–30 |
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