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CYRF69213 Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CYRF69213 Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 86 page  CYRF69213 Document Number: 001-07552 Rev. *H Page 7 of 86 PRoC LP Functional Overview The SoC is designed to implement wireless device links operating in the worldwide 2.4 GHz ISM frequency band. It is intended for systems compliant with worldwide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada) and TELEC ARIB_T66_March, 2003 (Japan). The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband performs Start of Frame (SOF), End of Frame (EOF) detection and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. The MCU function is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The instruction set has been optimized specifically for USB operations, although it can be used for a variety of other embedded applications. The MCU function has up to eight Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free-Running Timer, and 12-bit Programmable Interrupt Timer. The MCU function supports in-system programming by using the D+ and D– pins as the serial programming mode interface. The programming protocol is not USB. DDR Mode Table 1. DDR Mode Register Value Description TX_CFG_ADR 0X16 32 chip PN Code, DDR, PA = 6 RX_CFG_ADR 0X4B AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and the RX buffer is configured to receive eight bytes maximum. XACT_CFG_ADR 0X05 AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs. FRAMING_CFG_ADR 0X00 All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed. TX_OVERRIDE_ADR 0X04 Disable Transmit CRC-16. RX_OVERRIDE_ADR 0X14 The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the receiver accepts bad packets that do not match the seed in CRC_seed registers. Basically this helps in communication with the first generation radio that does not have CRC capabilities. ANALOG_CTRL_ADR 0X01 Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio. DATA32_THOLD_ADR 0X03 Sets the number of allowed corrupted bits to 3. EOP_CTRL_ADR 0x01 Sets the number of consecutive symbols for non correlation to detect end of packet. PREAMBLE_ADR 0xAAAA05 AAAA are the two preamble bytes.Other Bytes can also be written into the preamble register file. The number of preamble bytes to be sent should be >4. |
Similar Part No. - CYRF69213_13 |
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Similar Description - CYRF69213_13 |
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