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CYF0036V Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CYF0036V Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 36 page  CYF0018V CYF0036V CYF0072V Document Number: 001-53687 Rev. *M Page 9 of 36 Retransmit from Mark Operation The retransmit feature is useful for transferring packets of data repeatedly. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. Initiation of a retransmit operation (using RT pin) resets the internal read pointer to a physical location of the FIFO that is marked by the user (using the MARK pin). With every valid read cycle after retransmit, data is read out starting from the marked location and the read pointer is incremented until the FIFO is empty. Data written to FIFO after initiation of a retransmit operation are also transmitted. The full depth of the FIFO can be repeatedly retransmitted. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Refer to the latency table for the associated flag update latencies after initiation of a retransmit cycle. Asserting RT initiates a retransmit operation. The retransmit feature can be used when two or more data words have been written to the FIFO. When the MARK pin is asserted, the memory location corresponding to the data present on the output bus is marked. A mark operation is mandated prior to initiating a Retransmit operation. A retransmit operation should not be initiated when reads or writes are in progress. User should wait for four RCLK cycles after disabling reads before RT is asserted to ensure that the reads are completed. On initiation of RT the ‘marked’ location becomes the new Full Boundary. If user continues to write the data after initiation of a retransmit operation, FF will be asserted when this boundary is reached i.e. FF is asserted once the write pointer reaches the marked location.This prevents overwriting and data-loss. During RT reads the full boundary remains frozen to the marked location and is released when the FIFO becomes empty. i.e. FF remains LOW until the entire FIFO is read. Full flag is released LFF_RELEASE clocks after the EF is asserted. Full boundary is also released on a reset operation (MRS or PRS). Refer to Latency Table on page 16 for more details. Programming Flag Offsets and Configuration Registers The CYF0072V has ten 8-bit user configurable registers. These registers contain the almost-full (M) and almost-empty (N) offset values which decide when the PAF and PAE flags are asserted. These registers can be programmed in one of two ways: serial loading or parallel loading method. The loading method is selected using the SPI_SEN (Serial Enable) pin. A low on the SPI_SEN selects the serial method for writing into the registers. For serial programming, there is a separate SCLK and a Serial Input (SI). In parallel mode, a LOW on the load (LD) pin causes the write and read operation to these registers. The write and read operation happens from the first location (0x1) to the last location (0xA) in a sequence. If LD is HIGH, the writes occur to the FIFO. Register values can be read through the parallel output port regardless of the programming mode selected (serial or parallel). Register values cannot be read serially. The registers may be programmed (and reprogrammed) any time after master reset, regardless of whether serial or parallel programming is selected. Any changes to configuration registers during device operation mandates a PRS cycle to guarantee accurate flag operation. See Table 4 on page 11 and Table 5 on page 12 for access to configuration registers in serial and parallel modes. In parallel mode, the read and write operations loop back when the maximum address location of the configuration registers is reached. Simultaneous read and write operations should be avoided on the configuration registers. Any change in configuration registers will take effect after eight write clock cycles (WCLK) cycles. |
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