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CY22392SXI-xxx Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY22392SXI-xxx Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 13 page CY22392 Document Number: 38-07013 Rev. *I Page 6 of 13 Electrical Characteristics Parameter Description Conditions Min Typ Max Unit IOH Output High Current [4] VOH =VDD – 0.5 V, VDD =3.3 V 12 24 – mA IOL Output Low Current [4] VOL = 0.5 V, VDD =3.3 V 12 24 – mA CXTAL_MIN Crystal Load Capacitance [4] Capload at minimum setting – 6 – pF CXTAL_MAX Crystal Load Capacitance [4] Capload at maximum setting – 30 – pF CLOAD_IN Input Pin Capacitance [4] Except crystal pins – 7 – pF VIH High Level Input Voltage CMOS levels,% of AVDD 70% – – AVDD VIL Low Level Input Voltage CMOS levels,% of AVDD –– 30% AVDD IIH Input High Current VIN =AVDD –0.3 V – <1 10 A IIL Input Low Current VIN =+0.3 V – <1 10 A IOZ Output Leakage Current Three-state outputs – – 10 A IDD Total Power Supply Current 3.3 V Power Supply; 2 outputs at 166 MHz; 4 outputs at 83 MHz – 100 – mA 3.3 V Power Supply; 2 outputs at 20 MHz; 4 outputs at 40 MHz –50– mA IDDS Total Power Supply Current in Shutdown Mode Shutdown active – 5 20 A Switching Characteristics Parameter Name Description Min Typ Max Unit 1/t1 Output Frequency [4, 5] Clock output limit, Commercial – – 200 MHz Clock output limit, Industrial – – 166 MHz t2 Output Duty Cycle [4, 6] Duty cycle for outputs, defined as t2 t1, Fout < 100 MHz, divider > 2, measured at VDD/2 45% 50% 55% Duty cycle for outputs, defined as t2 t1, Fout > 100 MHz or divider = 1, measured at VDD/2 40% 50% 60% t3 Rising Edge Slew Rate [4] Output clock rise time, 20% to 80% of VDD 0.75 1.4 – V/ns t4 Falling Edge Slew Rate [4] Output clock fall time, 80% to 20% of VDD 0.75 1.4 – V/ns t5 Output three-state Timing [4] Time for output to enter or leave three-state mode after SHUTDOWN/OE switches – 150 300 ns t6 Clock Jitter [4, 7] Peak-to-peak period jitter, CLK outputs measured at VDD/2 – 400 – ps t7 Lock Time [4] PLL Lock Time from Power up – 1.0 3 ms Notes 4. Guaranteed by design, not 100% tested. 5. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications. 6. Reference Output duty cycle depends on XTALIN duty cycle. 7. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate. |
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