CY22392

Document Number: 38-07013 Rev. *I

Page 5 of 13

associated logic, while suspending an output simply forces a

tristate condition.

Improving Jitter

Jitter Optimization Control is useful in mitigating problems

related to similar clocks switching at the same moment, causing

excess jitter. If one PLL is driving more than one output, the

negative phase of the PLL can be selected for one of the outputs

(CLKA–CLKD). This prevents the output edges from aligning,

enabling superior jitter performance.

Power Supply Sequencing

sequencing requirements. The part is not fully operational until

the Operating Conditions. All grounds must be connected to the

same ground plane.

CyberClocks™ Software

The CyberClocks application enables users to configure this

device. Within CyberClocks, select the CyClocksRT tool. The

easy-to-use interface offers complete control of the many

features of this family including input frequency, PLL, output

frequencies, and different functional options. Data sheet

frequency range limitations are checked and performance tuning

is automatically applied. CyClocksRT also has a power

estimation feature that enables you to see the power

consumption of your specific configuration. Download a copy of

Install and run it on any PC running Windows.

Device Programming

Part numbers starting with CY22392F are ‘field programmable’

devices.

Field

programmable

devices

are

shipped

unprogrammed, and must be programmed prior to installation on

a PCB. After a programming file (.jed) is created using

CyberClocks software, devices can be programmed in small

quantities using the CY3672 programmer and CY3698 [1]

adapter. Volume programming is available through Cypress

Semiconductor’s value added distribution partners or by using

third party programmers from BP Microsystems, HiLo Systems,

and others. For sufficiently large volumes, Cypress can supply

pre-programmed devices with a part number extension that is

configuration-specific.

Junction Temperature Limitations

It is possible to program the CY22392 such that the maximum

junction temperature rating is exceeded. The package

115

C/W. Use the CyClocksRT power estimation feature to

verify that the programmed configuration meets the junction

temperature and package power dissipation maximum ratings.

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Supply Voltage .............................................–0.5 V to +7.0 V

Storage Temperature ............................... –65

C to +125 C

Junction Temperature ................................................ 125

C

Data Retention at Tj = 125

C ..............................> 10 years

Maximum Programming Cycles .......................................100

Package Power Dissipation ..................................... 350 mW

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ............................. 2000 V

Latch up (according to JEDEC 17) ..................... > ±200 mA

Operating Conditions

The following table lists the recommended operating conditions. [2]

Parameter

Description

Min

Typ

Max

Unit

Supply Voltage

3.135

3.3

3.465

V

Commercial Operating Temperature, Ambient

0

–

+70

C

Industrial Operating Temperature, Ambient

–40

–

+85

C

Maximum Load Capacitance

–

–

15

pF

External Reference Crystal

8

–

30

MHz

External Reference Clock [3], Commercial

1

–

166

MHz

External Reference Clock [3], Industrial

1

–

150

MHz

Power up time for all VDD's to reach minimum specified voltage

(power ramps must be monotonic)

0.05

–

500

ms

Notes

1. Programming of only 16-pin TSSOP package is supported by CY3698. For programming support of 16-pin SOIC package, contact your local FAE.

2. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.