CY14C101PA

CY14B101PA

CY14E101PA

Document Number: 001-54392 Rev. *L

Page 10 of 43

Status Register

The Status Register bits are listed in Table 2. The Status Register

consists of a Ready bit (RDY) and data protection bits BP1, BP0,

WEN, and WPEN. The RDY bit can be polled to check the

Ready/Busy status while a nvSRAM STORE or Software

RECALL cycle is in progress. The Status Register can be

modified by WRSR instruction and read by RDSR or

FAST_RDSR instruction. However, only the WPEN, BP1, and

BP0 bits of the Status Register can be modified by using the

WRSR instruction. The WRSR instruction has no effect on WEN

and RDY bits. The default value shipped from the factory for

WEN, BP0, BP1, bits 4–5, SNL and WPEN is ‘0’.

SNL (bit 6) of the Status Register is used to lock the serial

number written using the WRSN instruction. The serial number

can be written using the WRSN instruction multiple times while

this bit is still '0'. When set to ‘1’, this bit prevents any modification

to the serial number. This bit is factory programmed to ‘0’ and

can only be written to once. After this bit is set to ‘1’, it can never

be cleared to ‘0’.

Read Status Register (RDSR) Instruction

The Read Status Register instruction provides access to the

Status Register at SPI frequency up to 40 MHz. This instruction

is used to probe the Write Enable status of the device or the

Ready status of the device. RDY bit is set by the device to ‘1’

whenever a STORE or Software RECALL cycle is in progress.

The block protection and WPEN bits indicate the extent of

protection employed.

This instruction is issued after the falling edge of CS using the

opcode for RDSR.

Fast Read Status Register (FAST_RDSR) Instruction

The FAST_RDSR instruction allows you to read the Status

Register at SPI frequency above 40 MHz and up to 104 MHz

(max).This instruction is used to probe the Write Enable status

of the device or the Ready status of the device. RDY bit is set by

the device to ‘1’ whenever a STORE or Software RECALL cycle

is in progress. The block protection and WPEN bits indicate the

extent of protection employed.

This instruction is issued after the falling edge of CS using the

opcode for RDSR followed by a dummy byte.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status

Register. However, this instruction cannot be used to modify bit

used to select one of four levels of block protection. Further,

WPEN bit must be set to ‘1’ to enable the use of Write Protect

(WP) pin.

WRSR instruction is a write instruction and needs writes to be

enabled (WEN bit set to ‘1’) using the WREN instruction before

it is issued. The instruction is issued after the falling edge of CS

using the opcode for WRSR followed by eight bits of data to be

stored in the Status Register. WRSR instruction can be used to

modify only bits 2, 3, 6, and 7 of the Status Register.

Note In CY14X101PA, the values written to Status Register are

saved to nonvolatile memory only after a STORE operation. If

AutoStore is disabled, any modifications to the Status Register

must be secured by performing a Software STORE operation.

Table 2. Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPEN (0)

SNL (0)

X (0)

X (0)

BP1 (0)

BP0 (0)

WEN (0)

RDY

Table 3. Status Register Bit Definition

Bit

Definition

Description

Bit 0 (RDY)

Ready

Read only bit indicates the ready status of device to perform a memory access. This bit is

set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.

Bit 1 (WEN)

Write Enable

WEN indicates if the device is write enabled. This bit defaults to 0 (disabled) on power-up.

WEN = ‘1’ --> Write enabled

WEN = ‘0’ --> Write disabled

Bit 2 (BP0)

Block Protect bit ‘0’

Used for block protection. For details see Table 4 on page 12.

Bit 3 (BP1)

Block Protect bit ‘1’

Used for block protection. For details see Table 4 on page 12.

Bit 4–5

Don’t care

These bits are non-writable and always return ‘0’ upon read.

Bit 6 (SNL)

Serial Number Lock

Set to '1' for locking serial number

Bit 7(WPEN)

Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 5 on page 12.