CY8C20xx7/S

Document Number: 001-69257 Rev. *I

Page 9 of 43

24-pin QFN (16 Sensing Inputs)[11]

Table 3. Pin Definitions – CY8C20337, CY8C20347/S [12]

Pin

No.

Type

Name

Description

Figure 4. CY8C20337, CY8C20347/S Device

Digital Analog

1

I/O

I

P2[5] Crystal output (XOut)

2

I/O

I

P2[3] Crystal input (XIn)

3

I/O

I

P2[1]

4

IOHR

I

5

IOHR

I

6

IOHR

I

P1[3] SPI CLK

7

IOHR

I

MOSI

8

NC

No connection

9

Power

Ground connection

10

IOHR

I

CLK[14]

11

IOHR

I

P1[2] Driven Shield Output

(optional)

12

IOHR

I

P1[4] Optional external clock input

(EXTCLK)

13

IOHR

I

P1[6]

14

Input

XRES Active high external reset

with internal pull-down

15

I/O

I

P2[2] Driven Shield Output

(optional)

16

I/O

I

P2[4] Driven Shield Output

(optional)

17

IOH

I

P0[0] Driven Shield Output

(optional)

18

IOH

I

P0[2] Driven Shield Output

(optional)

19

IOH

I

P0[4]

20

Power

Supply voltage

21

IOH

I

P0[7]

22

IOH

I

P0[3] Integrating input

23

Power

Ground connection

24

IOH

I

P0[1] Integrating input

CP

Power

Center pad must be

connected to ground

LEGEND

A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

QFN

(Top View)

AI, I2C SCL, SPI SS, P1[7]

AI, I2C SDA, SPI MISO, P1[5]

AI, SPI CLK, P1[3]

1

2

3

4

5

6

18

17

16

15

14

13

P0[0], AI

P2[4], AI

P0[2], AI

AI, P2[1]

P1[6], AI

XRES

P2[2], AI

AI, XOut, P2[5]

AI, XIn, P2[3]

Notes

it must be electrically floated and not connected to any other signal.

13. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

alternate pins if you encounter issues.

14. Alternate SPI clock.