CY8C20xx7S datasheet(4/43 Pages) CYPRESS

Part #	CY8C20xx7S

Description	1.8 V CapSense짰 Controller with SmartSense??Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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4 / 43 page

CY8C20xx7/S

Document Number: 001-69257 Rev. *I

Page 4 of 43

PSoC® Functional Overview

The PSoC family consists of many devices with on-chip

controllers. These devices are designed to replace multiple

traditional MCU-based system components with one low-cost

single-chip programmable component. A PSoC device includes

configurable blocks of analog and digital logic, and

programmable interconnect. This architecture makes it possible

for you to create customized peripheral configurations, to match

the requirements of each individual application. Additionally, a

fast central processing unit (CPU), flash program memory,

SRAM data memory, and configurable I/O are included in a

range of convenient pinouts.

The architecture for this device family, as shown in the Logic

Block Diagram on page 2, consists of three main areas:

■ The core

■ CapSense analog system

■ System resources

A common, versatile bus allows connection between I/O and the

analog system.

Each CY8C20x37/47/67/S PSoC device includes a dedicated

CapSense block that provides sensing and scanning control

circuitry for capacitive sensing applications. Depending on the

PSoC package, up to 34 GPIOs are also included. The GPIOs

provide access to the MCU and analog mux.

PSoC Core

The PSoC core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO and

ILO. The CPU core, called the M8C, is a powerful processor with

speeds up to 24 MHz. The M8C is a 4-million instructions per

second (MIPS), 8-bit Harvard-architecture microprocessor.

CapSense System

The analog system contains the capacitive sensing hardware.

Several hardware algorithms are supported. This hardware

performs capacitive sensing and scanning without requiring

external components. The analog system is composed of the

CapSense PSoC block and an internal 1 V or 1.2 V analog

reference, which together support capacitive sensing of up to 31

inputs[3]. Capacitive sensing is configurable on each GPIO pin.

Scanning of enabled CapSense pins is completed quickly and

easily across multiple ports.

SmartSense™ Auto-tuning

SmartSense auto-tuning is an innovative solution from Cypress

that removes manual tuning of CapSense applications. This

solution is easy to use and provides robust noise immunity. It is

the only auto-tuning solution that establishes, monitors, and

maintains all required tuning parameters of each sensor during

run time. SmartSense auto-tuning allows engineers to go from

prototyping

to

mass

production

without

retuning

for

manufacturing variations in PCB and/or overlay material

properties.

Figure 1. CapSense System Block Diagram

Analog Multiplexer System

The analog mux bus can connect to every GPIO pin. Pins are

connected to the bus individually or in any combination. The bus

also connects to the analog system for analysis with the

CapSense block comparator.

Switch-control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

■ Complex capacitive sensing interfaces, such as sliders and

touchpads.

■ Chip-wide mux that allows analog input from any I/O pin.

■ Crosspoint connection between any I/O pin combinations.

IDAC

Reference

Buffer

Vr

Cap Sense Counters

Comparator

Mux

Refs

CapSense

Clock Select

Oscillator

CSCLK

IMO

CS1

CS2

CSN

Cexternal (P0[1]

or P0[3])

Note

3. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.

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CY8C20xx7S Datasheet(PDF) 4 Page - Cypress Semiconductor

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