CY7C1474V33-200BGC datasheet(10/38 Pages) CYPRESS

Part #	CY7C1474V33-200BGC

Description	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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10 / 38 page

CY7C1470V33

CY7C1472V33

CY7C1474V33

Document Number: 38-05289 Rev. *S

Page 10 of 38

and CE3 are all asserted active, and (3) the write signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the address register. The write signals are latched

into the control logic block.

On the subsequent clock rise the data lines are automatically

tristated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V33,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for

CY7C1472V33). In addition, the address for the subsequent

access (read/write/deselect) is latched into the address register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V33,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for

CY7C1472V33) (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the write is complete.

The data written during the write operation is controlled by BW

(BWa,b,c,d,e,f,g,h for CY7C1474V33, BWa,b,c,d for CY7C1470V33

and BWa,b for CY7C1472V33) signals. The CY7C1470V33,

CY7C1472V33,

and

CY7C1474V33

provides

byte

write

capability that is described in the Write Cycle Description table.

Asserting the write enable input (WE) with the selected byte write

select (BW) input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self timed Write mechanism has been

provided to simplify the write operations. Byte write capability

has been included in order to greatly simplify read/modify/write

sequences, which can be reduced to simple byte write

operations.

Because

the

CY7C1470V33,

CY7C1472V33,

and

CY7C1474V33 are common I/O devices, data should not be

driven into the device while the outputs are active. The output

enable (OE) can be deasserted HIGH before presenting data to

the

DQ

and

DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and

DQa,b/DQPa,b for CY7C1472V33) inputs. Doing so will tristate

the output drivers. As a safety precaution, DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V33,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for

CY7C1472V33) are automatically tristated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an

on-chip burst counter that allows the user the ability to supply a

single address and conduct up to four write operations without

reasserting the address inputs. ADV/LD must be driven LOW in

order to load the initial address, as described in the Single Write

Accesses section above. When ADV/LD is driven HIGH on the

subsequent clock rise, the chip enables (CE1, CE2, and CE3)

and WE inputs are ignored and the burst counter is incremented.

The correct BW (BWa,b,c,d,e,f,g,h for CY7C1474V33, BWa,b,c,d for

CY7C1470V33 and BWa,b for CY7C1472V33) inputs must be

driven in each cycle of the burst write in order to write the correct

bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ

 V

DD 0.2 V

–

120

mA

tZZS

Device operation to ZZ

ZZ

 V

DD  0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ

 0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

–

ns

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CY7C1474V33-200BGC Datasheet(PDF) 10 Page - Cypress Semiconductor

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