CY7C1480V33_13 datasheet(11/25 Pages) CYPRESS

Part #	CY7C1480V33

Description	72-Mbit (2 M x 36) Pipelined Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1480V33

Document Number: 38-05283 Rev. *N

Page 11 of 25

ISB3

Automatic CE Power Down

Current – CMOS Inputs

VDD = Max, Device Deselected,

VIN  0.3 V or VIN > VDDQ – 0.3 V,

f = fMAX = 1/tCYC

5.0-ns cycle,

200 MHz

–245

mA

6.0-ns cycle,

167 MHz

–245

mA

ISB4

Automatic CE Power Down

Current – TTL Inputs

VDD = Max, Device Deselected,

VIN  VIH or VIN  VIL, f = 0

All speeds

–

135

mA

Electrical Characteristics (continued)

Over the Operating Range

Parameter [10, 11]

Description

Test Conditions

Min

Max

Unit

Capacitance

Parameter [12]

Description

Test Conditions

100-pin TQFP

Max

Unit

CADDRESS

Address input capacitance

TA = 25 C, f = 1 MHz,

VDD = 3.3 V, VDDQ = 2.5 V

6pF

CDATA

Data input capacitance

5pF

CCTRL

Control input capacitance

8pF

CCLK

Clock input capacitance

6pF

CI/O

Input/Output capacitance

5pF

Thermal Resistance

Parameter [12]

Description

Test Conditions

100-pin TQFP

Package

Unit



JA

Thermal resistance

(junction to ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, according

to EIA/JESD51.

24.63

C/W



JC

Thermal resistance

(junction to case)

2.28

C/W

Note

12. Tested initially and after any design or process change that may affect these parameters.

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CY7C1480V33 Datasheet(PDF) 11 Page - Cypress Semiconductor

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